Fullscreen HTML5Med Res (??MB)HTML4

USB Part 2 By Phil Prosser Last month, we introduced our new USB SuperCodec sound card design, which boasts superb recording and playback performance. It isn’t only useful for recording and playback though; with some inexpensive software, it can make a very advanced audio signal analysis system. Now it’s time to describe the details of the circuitry behind its phenomenal performance. W e covered the basic operating principles of the USB SuperCodec in last month’s introductory article, but we ran out of space to fit the full circuit details. As you will see from this article, that’s mainly due to the number and size of the circuit diagrams. Since the circuit of the USB SuperCodec is too large to fit across two pages, we have broken it up into five sections: the computer interface with galvanic isolation (Fig.12), local clock generation and asynchronous sampling rate conversion (Fig.13), the ADC section (Fig.14), the DAC section (Fig.15) and the power supply (Fig.16). Galvanic isolation The galvanic isolation is provided by IC12, a Maxim MAX22345 (see Fig.12). This is a fast, low-power, fourchannel galvanic isolator chip. We are using the 200Mbps version as we wanted to be able to transfer clock signals at more than 12MHz (the bit clock [BCLK]) and 24MHz (the master clock [MCLK]). The version that we are using provides three ‘left to right’ and one ‘right to left’ channels. This is ideal for isolating the I2S output from the MCHStreamer. When we had the computer ground electrically connected to the USB sound card ground in a real-world system, we found it impossible to get rid of residual 50Hz-related noise and a bunch of ‘spurs’ in the noise floor. While these were low enough to be inaudible, putting the galvanic isolation into the system saw these drop significantly. Indeed, even allowing the USB earth to connect to the case of the USB SuperCodec increased the 50Hz hum by 10-20dB! This chip is not that expensive, but the benefit of using it as part of a measurement system is huge. USB3.3V I S data OUT Ch1&2 2 J1 26 51 1 2 1 J2 10 7 2 2 USB BCLK (VIA CON2) (VIA CON3) 1 I S data IN Ch1&2 12 1 76 100nF OPTICAL INPUT MINIDSP MCHSTREAMER MODULE USB TYPE B DVDD3.3V 2 OUT1 18 MINIDSP I2S_DAC 4 IN2 OUT2 17 MINIDSP B CLK 5 IN3 OUT3 16 MINIDSP LRCLK 6 OUT4 IN4 15 MINIDSP I2S_ADC1 9 USB LRCLK VDDB 14 DEFB 3 IN1 8 OPTICAL OUTPUT 1 J3 IC12 MAX22345 20 VDDA DEFA DVDD3.3V 100nF 2 ENA ENB NC NC GNDA GNDA GNDB GNDB 10 11 13 12 19 RESET_L 10k USB GND 3 USB3.3V BC549 VCC DS1233 B E USB3.3V 1k OPTO1 4N28 6 1 2 C 2  5 4 C B Q1 BC549 RESET IC13 DS1233 GND 1 E 3 2 1 SC  SuperCodec (USB Sound Card) MiniDSP MCH Streamer and Galvanic Isolation Circuitry 2020 Fig.12: this section of the full circuit connects the MCHStreamer to a MAX22345 high-speed isolator and a bogSUPERCODEC (USBTheSOUND CARD) MiniDSP MCH Streamer & Galvanic Isolation Circuitry standard 4N28 optocoupler. latter releases the ADC and DAC reset lines 350ms after plugging in USB. 24 Practical Electronics | October | 2021 We must make it clear that while this device provides a high degree of isolation, we have not designed the circuit board to handle significant voltage differences between the two domains. Do not, in any circumstances, rely on this design to provide safety isolation between the PC and the sound interface! It is purely intended to improve the performance, and allow a few volts of difference between your computer and audio grounds, as can sometimes occur. The data rates from the USB interface are quite high. The MCLK signal is at 24.576MHz for the 192kHz sampling rate, and the BCLK is half this, at 12.288MHz. Design and layout of a board for reliable operation at 25MHz requires attention to detail, careful grounding and termination for long traces. We have used series termination on the 25MHz clock signal, and managed to keep high-speed traces tidy and with a minimum of vias. They all run over a solid ground plane for their entire length. Where we have had to route across these signals, we made the aperture in the ground plane as small as possible. We came close to using a four-layer PCB for this design, but by constraining the digital signals to a limited area, and with careful layout, we have avoided the cost this would incur. In the final version of the design, we are using a local clock oscillator for the 24.576/25MHz clock, so while we can access the master clock from the MiniDSP MCHStreamer, it is not used, as we can do better with a local clock source. Hence, Fig.12 does not show any connection to the MCLK pin of the MCHStreamer module. In case you’re wondering how the MAX22345 works, isolators like this generally get the signal across the isolation barrier using either magnetic or capacitive coupling (high-speed optical isolators exist but are usually bulkier). Maxim does not explicitly state which, but it appears to be capacitive. We’re also using an ordinary old 4N28 optocoupler. This tells the audio side whether or not power being received from the computer. If there is no power, the ADC and DAC are held in reset. Once there is 3.3V power from the USBStreamer, the ADC and DAC are taken out of reset after 350ms. The DS1233 provides this delay; the signals from the USB Streamer should have stabilised after 350ms. From a user’s perspective, this means that when you plug the USB SuperCodec in, it looks after its own reset and ‘just works’. Local clock generation and ASRC This section has been the subject of a lot of work. It would be possible to drive the ADC and DAC directly from the miniDSP MCHStreamer, as isolated by the MAX22345. But what if the user wants to operate the card at 44.1kHz, 48kHz, 96kHz, 192kHz or some other rate? How do the ADC and DAC get set up for this? The CS4398 and CS5381 chips both have mode pins that must be set depending on the sampling rate at which we want to operate. Practical Electronics | October | 2021 In the prototype, we used jumpers to set the sampling rate for the ADC and DAC. We quickly decided that users will want to plug the card in and have it sort this out for itself. It would be possible to, say, use a microcontroller to sense the sampling rate and set the chips up accordingly. But there is a better way – using a device called an asynchronous sampling rate converter (ASRC). ASRCs are found in professional recording studios and also consumer equipment which have digital-audio-todigital-audio interfaces. Imagine you have two digital audio devices, say an amplifier and a CD player. Each is a standalone device with its own clocks and generally looks after itself. When We’ll get onto the construction next month, after we’ve finished with the rather involved description. To whet your appetites, here’s the completed PCB mounted on the input/output socket, shown life size. 25 Fig.13: the ASRC circuitry sits in between the galvanic isolation section and the ADC and DAC chips. Its job is to pass digital audio data between two clock domains: that of the USB MCHStreamer, with a nominal 24.576MHz master clock, and the ADC and DAC, clocked by 25MHz crystal oscillator module XO1. The relative drift of these two clocks is taken care of by the digital filters in IC6 and IC7. Supercodec (USB Sound Card) Sample Rate Converter Circuitry you plug these together, if you want to have the CD player provide digital data to the amplifier, what happens if (as is inevitable), the CD player’s clock is just slightly different in frequency to the clock in the amplifier? Eventually, the CD player will provide either too much or too little data to the amplifier. In serious situations (eg, professional mixing rigs), you can have a master clock distribution system. But most devices don’t have provision for that. Alternatively, you can use an ASRC. Instead of locking the clocks of different chips together, the ASRC flips the problem on its head. It allows our ADC and DAC to have their own clocks, and does a bunch of maths to pass the correct digital values to and from the computer at whatever sampling rate it happens to be running at. This involves the ASRC monitoring the different sampling rates, then implementing digital filters to deliver the exact digital value needed at every sample interval. The upshot of this is that we can use a local 25MHz clock source to drive both the ADC and DAC. The clock we have chosen is good without getting silly. Its typical RMS jitter is less than 1ps (one million millionth of a second!). You 26 could go for a better unit, but our analysis suggests that the difference would be essentially unmeasurable. Indeed using a ‘better’ clock is a tweak that some serious audiophiles do. We have used a sample rate converter in each of the ADC and DAC lines, as we need to perform this translation for both recording and playback. The devices we’re using are both Cirrus Logic CS8421s. If you are worried about what these things may do to the sound, fear not. These are rated for 175dB dynamic range and –140dB (0.00001%) THD+N! So the impact of these devices is so low that it is not at all detectable, let alone audible. (We have donned our asbestos underwear as we await the flame throwers of the anti-ASRC audiophile crowd!) The actual implementation of these chips is not complex, as shown in Fig.13. The digital audio signals go into pins 7, 8 and 9 at one particular sampling rate and emerge from pins 12, 13 and 14 at a different rate, to match up with the clock signal applied to pins 2. Using an ASRC has a couple of implications on how the ADC and DAC are set up and driven. Practical Electronics | October | 2021 First, we must provide a low-noise clock. This is from XO1, a 25MHz clock oscillator module. Second, we need the local left/right clock (ie, sampling rate) at a higher rate than the 192kHz that the MiniDSP USBStreamer uses, to ensure no degradation of the digital signal. 25MHz divided by 32 (bits each in the L and R samples) divided by 2 then 2 again is 195.3125kHz. So that suits us fine. We need to set the ASRC for the CS4398 DAC as a master output so that it generates the 195.3125kHz left/right clock (LRCK) and control signals for this ADC on its output – ie, the ASRC drives the DAC at this rate at all times. We need the ASRC for the CS5381 ADC as a master input so that it generates the 195.3152kHz clock and control signals for the MCHStreamer on its input. Pin 6 ( BYPASS) allow the ASRC action to be disabled, but since we always want it active, we have tied this to GND. Similarly, we are not using the Time Domain Multiplexing (multi-channel) feature, so pins 11 are tied low. The MS_SEL pin of IC6 is pulled down via a 2kΩ resistor, which sets the device to slave mode on its input side (clocks are inputs), and master mode on its output side (clocks are outputs). The 1kΩ resistor from pin 19 (SAIF) to ground sets the inputs of both devices to 32-bit I2S mode; one of six different digital audio protocols this chip supports. This matches the data format from the MCHStreamer. Similarly, the 4kΩ total resistance from pins 18 (SAOF) to ground sets the output side to I2S mode with 24-bit data, to suit our ADC and DAC chips. This is one of 16 possible formats the chip supports. Once set up as above, this forms a neat interface between parts of a system that may have differing clocks. Is there a downside? They are not cheap devices, but we think they’re worth it for the flexibility they provide. Analogue-to-digital conversion We’re using the CS5381-KZZ chip. Cirrus Logic make two similar devices, the CS5361 and CS5381. They are pin-compatible, but the CS5381 has better distortion performance. We have specified the better of the two. You could drop in the CS5361 instead, and will lose a bit of performance on the input channels. The circuitry surrounding this chip, shown in Fig.14, is close to what is recommended by the Cirrus Logic application note. However, we have gone to extra lengths to ensure very symmetrical drive of the input, and to make sure that the sound card has a high-impedance input. Ferrite beads FB3 and FB4, with the following 100pF capacitors to ground, form RF filters at the inputs. Bipolar electrolytic capacitors block DC voltages, with a –3dB cutoff well below 1Hz. Schottky diodes D5, D10, D15 and D16 protect the op amp inputs against spikes and excess voltage. In normal operation, these do not affect the signal. IC2a/IC4a operate as unity-gain buffers. They provide a low-impedance drive for the following two stages without SOURCING THE COMPONENTS Some of the components for this project are rather specialised and might be difficult to track down. To assist you in this endeavour, we have produced a spreadsheet which gives catalogue codes for each part needed, from six different sources: • Altronics • Jaycar • Digi-Key • Mouser • element14 • RS You’ll find this spreadsheet at: https://bit.ly/pe-oct21-codec Practical Electronics | October | 2021 affecting the input. IC2b/IC4b operate as inverters. We have used 1.2k feedback resistors, as low as practical, to keep noise down while allowing the operational amplifier to drive the following stage without any concern of increasing distortion by overloading the output. We could have gone a touch lower in resistance, but feel this is a good compromise on performance and power use. IC3a/IC5a and IC3b/IC5b drive the differential inputs of the ADC, and all four stages are configured in a very similar manner. There are a couple of things going on here. The non-inverting inputs are held at a 2.5V bias via 10kΩ resistors from IC1’s VQ (quiescent voltage) pin, pin 22. These resistors have 10nF local bypass capacitors to ensure the op amps see a very low source impedance. The inverting inputs of these op amps are driven by the in-phase and inverted signals from the previous stage, which are capacitively-coupled to support the DC offset. You might be concerned that the input signal could affect the 2.5V, but these signals are balanced, so their effects on the reference voltage essentially cancel out. The 470pF feedback capacitors form low-pass filters in combination with the 680Ω and 91Ω resistors. This has a cutoff way above the audio band, at around 500kHz, to ensure stability and get rid of any RF noise which makes it past the input filter. Note that at audio frequencies, these four stages form unity-gain buffers. The fact that the output is taken from the junction of the resistors reduces transient loading on the operational amplifier. Some low-pass filtering is provided by the combination of these resistors and the 2.7nF capacitors across the pairs of differential ADC input pins. These capacitors are mounted very close to the input pins. Our testing showed that these capacitors are critical to the performance of the ADC. Do not use any old capacitor. Do not use an ‘audiophile’ capacitor. Do use a ceramic NP0 or C0G type capacitor, surface mounting, of known provenance. We built a prototype with a film capacitor here, and the distortion went up by a factor of ten. We also tried silver mica caps, and they were no better. Clearly, it isn’t just the linearity of this capacitor that is critical; the oversampling ADC draws pulses of current from these caps at a high frequency, so we need caps with a low ESR at several megahertz, as well as linearity. Only NP0/C0G ceramics provide both. The ADC input pins have BAT85 diodes to each rail for protection. Reviewing the data sheet, it seems that the ADC should survive the maximum output current of a NE5532, but it might not survive the maximum output current of an LM4562. We suspect that some people might try different op amps – and since IC1 costs around £27.50 (!) – it’s worthwhile providing protection. The VA analogue supply to IC1 is nominally 5V, and we have a local low-dropout linear regulator (REG5) to provide a 3.3V digital logic supply rail for IC1. We have done this locally as it draws little current and made the layout so much easier. Pin 15 of the ADC provides an overflow indication. This drives the LED on the front of the unit. Should this flash during operation, you are driving the ADC into clipping, and need to lower the input level. Generally, you should be running the input substantially lower than this. The noise and distortion are optimal at a decibel or so below clipping, and even if you run this 10dB lower, the impact on performance will be minimal. The ADC pins at upper right are tied either to VL or GND to set it up in ‘hardware mode’ (ie, not being controlled by a microcontroller), with the correct audio format selected. The digitised audio signals appear at pin 9 of IC1 and goes onto ASRC IC7, as shown in Fig.13. That same ASRC chip and XO1 provide the clock signals at pins 3, 4 and 5 of IC1. 27 Digital-to-analogue conversion The CS4398 DAC is configured in a fairly conventional manner – see Fig.15. Discussing the right channel, IC9’s differential outputs drive two low-pass filters formed by IC8a and IC8b. The filter on each pin is set up to present the same load to the two outputs. The impedances have been kept low to minimise noise. This filter is the same as used in the DSP Crossover (PE, January – March 2020) and limits the output of supersonic signals. We have specified C0G ceramic capacitors (or NP0; same thing) where ceramic types are used. This is very important as other dielectrics will introduce more distortion. For the 1.5nF, 10nF and 22nF capacitors we used MKT capacitors. The selfresonance of low-value MKTs is typi- cally in the 10MHz region, so the filter behaved well and provided excellent performance. They are easier to obtain than NP0/C0G ceramics with those same values, so you might as well stick with the MKTs. But if you use very highspeed op amps in place of the NE5532s, things could change. IC10b forms a differential-to-singleended signal converter. The 1.2kΩ resistor values are low enough to minimise noise while not overloading the op amp, and leave headroom for it to drive a load. The 470pF capacitors in this stage form the final stage of the low-pass filter. The DC output level of the DAC is 2.5V. This runs through the filters formed by IC8a and IC8b. Rather than AC-coupling the signal to the differential to single-ended converter, we have used the converter to remove the bulk of the DC offset itself. The AC-coupling capacitor at its output removes any residual DC – though in our prototype, this was a very low level. The power supply The power supply, shown in Fig.16, may look over the top. This design makes no apology for taking power supplies and grounding to something of an extreme as we aim to deliver solid ADC and DAC performance, at the parts-permillion level. In particular, any noise on the +5VA rail is a very bad thing, and we want the +5VL and ±9V rails to be clean of noise and clocking artefacts. The first version of this unit used a toroidal transformer mounted on the opposite side of the case from the sensitive analogue parts. It even included a copper shorting ring to reduce radi-                            SCSupercodec SUPERCODEC(USB (USBSound SOUNDCard) CARD)  28 Analogue-to-Digital Converter Circuitry Practical Electronics | October | 2021 ated noise. Even so, we could still see the 50Hz leaking into the plots down around the –110 to –130dB levels. So we changed it to run off a single +12V DC plugpack. It uses two LM2575 buck regulators (REG1 and REG2) to generate a +6.5V DC rail and –12V DC rail. This choice might raise a few eyebrows as switchmode converters are not famous for low levels of radiation. And you may wonder how the same chip is used to generate both positive and negative rails. Let’s start with that negative rail. In essence, we are turning REG2 on its head; its positive output connects to GND (after the LC filter), while its GND pin is actually ‘floating’ on the negative rail! It may seem strange, but if you analyse the circuit carefully, you will see that this will work. But there are a few things you need to be aware of when using a buck regulator this way. On startup, it tends to draw a lot of current for a short period. The Texas Instruments data sheet warns of this, and they were right to! The peak startup current is about 2A, so be sure to use the recommended plugpack, or check that yours works OK. There is also an LM2576, which is a beefier version of the LM2575. This draws closer to 4.5A on startup. It works, but watch that startup current. So how does this work? Here’s a brief explanation: REG2 ‘tries’ to keep the feedback voltage at pin 4 about 1.25V above its ground pin, pin 3. As the –12V rail is initially at 0V, so is pin 4, so the output switches on hard. This means that current can pass from the 12V input, through inductor L3 and to ground.     www.poscope.com/epe - USB - Ethernet - Web server - Modbus - CNC (Mach3/4) - IO   - PWM - Encoders - LCD - Analog inputs - Compact PLC  - up to 256 - up to 32 microsteps microsteps - 50 V / 6 A - 30 V / 2.5 A - USB configuration - Isolated PoScope Mega1+ PoScope Mega50    Fig.14: the stereo analogue audio signals applied to RCA sockets CON6a and CON6b are buffered and pass through a series of RF filters before being converted to balanced (differential) signals, which are then fed to the pairs of ADC inputs at pins 16/17 and 20/21 of IC1. The 2.7nF filter capacitors are critical to getting good results, while numerous schottky diodes protect the various ICs from signal overload. Practical Electronics | October | 2021 - up to 50MS/s - resolution up to 12bit - Lowest power consumption - Smallest and lightest - 7 in 1: Oscilloscope, FFT, X/Y, Recorder, Logic Analyzer, Protocol decoder, Signal generator 29 Tweaking the SuperCodec’s performance Phil Prosser delivered a prototype to us with excellent performance. However, on measuring its performance, we detected an anomaly. The DAC THD+N figure increased for test frequencies below 200Hz, rising from 0.00054% at 1kHz to around 0.00085% at 20Hz. This was not what we expected, as performance usually improves as the test signal frequency drops. At first, we suspected that the 22µF bipolar output coupling capacitors could be the culprits, as rising distortion with decreasing frequency is a signature of coupling-capacitor-induced distortion. However, replacing these with 100µF high-quality devices (which you may have noticed in our photographs) failed to yield any improvement. This led us to suspect that the lowfrequency signal was modulating a voltage rail, so we turned our attention to the capacitors surrounding the CS4398 DAC, IC9. The most critical capacitors are the electrolytic filter capacitor on pin 26, VQ, which stabilises the half-supply rail (quiescent output voltage, hence VQ); the 33µF filter capacitor at pin 17 (VREF), which also helps to smooth the VA (analogue supply voltage) 5V rail that it’s connected to; and the electrolytic capacitor at pin 15 (FILT+). The capacitor from pin 26 to ground was originally 3.3µF. After soldering a 47µF capacitor across it, we re-tested the unit and found two things. One, it took a lot longer to reach normal operating conditions (presumably the larger capacitor takes longer to charge). And two, while the THD+N figures did drop around 25% at lower frequencies (and a bit across the board), there was still a rise in distortion below 200Hz. Adding a 470µF capacitor from pin 17 (VREF) to ground did nothing, indicating that this rail was sufficiently noise-free. But moving that capacitor to go from pin 15 (FILT+) to ground, which originally had a 100µF in parallel with the 100nF, totally eliminated the rise in distortion at lower frequencies and also slightly lowered distortion across the board. So we decided to compromise with the VQ filter capacitor at 10µF; higher than the original 3.3µF for improved overall performance, but not so high that the unit takes ages to stabilise when powered on. And we definitely upgraded the 100µF capacitor at the FILT+ pin to a high-quality 470µF unit, which just fits, as this was the ‘cherry on top’ in terms of obtaining the ultimate performance. The regulator switches its output in pulses at about 50kHz. When it switches off, the inductor’s magnetic field causes current to continue to flow. This can no longer come from the LM2575, so the voltage at pin 2 drops and the current flows from the negative pin of the output capacitor, through D3. As a result, the voltage across the output capacitor increases, meaning its negative end gets more negative. This cycle continues, with the capacitor charging further, resulting in the ground pin falling negative relative to the output. As the voltage across the feedback divider is increasing, the voltage at feedback pin 4 relative to pin 3 also increases. Eventually, the capacitor is charged to 12V, and the ground pin is now 12V below the feedback pin. Pin 4 is then at around –10.75V, ie, 1.25V above pin 3. The regulator then operates normally, varying its mark to space ratio to keep this voltage as required. The regulator is essentially driving a short-circuit at startup, hence the fairly impressive but brief initial current demand.                  SCSupercodec (USB Sound Card) Digital-to-Analogue Converter Circuitry SUPERCODEC (USB SOUND CARD)  30 Practical Electronics | October | 2021 Still using the NE5532 – really? We have specified NE5532 op amps for this project. This may be a point of contention with some readers. We built eight of the DAC modules as used in the DSP Active Crossover, allowing a comparison of NE5532 and LM4562 devices, and were unable to conclusively measure one as better than the other. We expect that we were measuring the actual ADC and DAC performance. Given that the LM4562 costs more than the NE5532 (and consumes more power) there seemed to be no good reason to use them. We have also used LM833 op amps; they work too, but not as well; they can’t drive as low impedances as NE5532s, so require more of a distortion/noise tradeoff. If you have a favourite op amp that you want to use, we recommend you install high quality machined sockets, as desoldering op amps from a double-sided PCB generally kills the op amp, and may damage the PCB. (Suitable sockets are the Altronics P0530 or similar). Things you would need to check if you do this include oscillation, ringing and leakage of high-frequency products from the DAC to the output. We also suspect that you will, in the best case, get equivalent performance, and quite possibly worse. If you want to get the rated performance, it’s best to stick with the devices that we tested! To keep radiated noise from the switchmode supplies low, we have been rather careful with the layout, making sure current loops are small. We have also used low-ESR capacitors throughout, as well as oversized toroidal inductors. This contains the magnetic field inside the inductors and avoids saturation, which would lead to increased radiation. The switchmode supplies are also located as far from the low-level analogue electronics as we can manage. On our test plots, there is a tiny bit of noise visible around the 50kHz operating frequency, but it’s so low that it doesn’t matter. Also, that’s above the range of our hearing, a fact that is no coincidence. We used a large output capacitor of 2200µF to minimise noise. Then we added a 47µH/100µF LC low-pass filter to reduce noise at the output further. At this point, the ripple on the supply rail is only a few millivolts. The +6.5V supply is provided by a conventional implementation of a buck regulator, using REG1. Again, we have put in a 2200µF filter capacitor and 47µH/100µF post-regulator filter. This also uses low-ESR capacitors. Why 6.5V? One problem you find with high-speed logic is that it can draw a fair current from low-voltage rails. We do not want to use a linear regulator to generate a 2.5V or 3.3V rail that might have to deliver 100-200mA. We would need to dissipate 1.7W: (12V – 3.3V) ×0.2A. This is possible, but is a real nuisance to dissipate in a small enclosure. So instead, we are using switchmode regulators to generate +6.5V and –12V rails, and then feeding these into four linear regulators to produce very clean +5V, +3.3V, +2.5V, +9V and –9V supplies for the ICs. The input of each linear regulator is fed through a ferrite bead, to minimise the chance of any RF type signals passing through the regulator. The +12V and –12V ‘noisy’ rails are regulated to +9V and –9V using LM317 and LM337 adjustable regulators. These have especially good ripple and noise rejection. The ±9V rails power the op amps for the ADC and DAC sections. Note that there is a further RC filter in the ADC and DAC domains, formed by 10Ω resistors and 47µF capacitors, to ensure isolation between the ADC and DAC supply rails. A low-dropout AZ1117H regulator is used to generate the +5V VA rail. This is a low-noise rail, and if you analyse the PCB, you will find that it is routed away from the digital section. The DVDD +3.3V and VD +2.5V rails are for digital purposes, and use ordinary LM317 devices.     PCB layout trick We’ll be presenting the PCB design next month, along with the PCB assembly, testing and wiring instructions. But there are a few performance-related things to consider about the PCB, which we’ll briefly mention before signing off. With the power supply at the bottom, all the digital signals and power supplies run up the left-hand side of the board, and the low noise and analogue signals up the right-hand side. This is         Next month . . .    Fig.15: IC9 converts the digital audio signals from the ASRC stage to balanced analogue outputs at pin pairs 19/20 and 23/24. These are then filtered to remove digital artefacts and converted to single-ended audio, to be fed to RCA output sockets CON7a and CON7b. Practical Electronics | October | 2021 In the third and final article next month we’ll have all the construction details, plus the test procedures after each stage of construction, to ensure that everything is working correctly before you proceed to the next step. We’ll then cover a final set of tests; how to download, install and set up the USB drivers, and some useful information on using the finished product. 31                                           SCSupercodec (USB Sound Card) Power Supply Regulators SUPERCODEC (USB SOUND CARD)  Fig.16: the power supply circuitry efficiently produces five very clean supply rails from the possibly noisy 12V DC input. These are ±9V for the op amps, +5V for the ADC and DAC chips, +3.3V for the digital section of the DAC chip and the two ASRC chips (IC6 and IC7) plus the isolator (IC12) and +2.5V for DC-biasing the analogue signals fed to the ADC. The ADC also has a local regulator (REG5) to produce its 3.3V digital rail from the +5V rail, as it was easier to lay out the board that way. intentional, to maintain isolation between these domains. The switchmode section that generates the –12V and –6.5V rails has a separate ground plane. At the output of this are the final 47µH/100µF filters. After that, there is a wire jumper from the ‘noisy ground’ at the input to the larger ground plane for the linear regulators. The aim here is to avoid allowing currents in the ‘noisy ground’ injecting noise into the remainder of the circuit. 32 There is also a vertical cut on the left-hand side of the ground plane which isolates the digital section from the power supplies. This ensures that the digital circuitry is operating in a ground plane largely separated from the analogue section, with the ‘connection’ being around the DVDD +3.3V output. The aim is to avoid the digital circuitry injecting noise onto the analogue ground plane. There is a ground plane across almost the entirety of the top of the board (bottom under the digital section), and ground fills everywhere practical. So here we have a range of low-noise, carefully isolated power supplies that are distributed in a manner to minimise contamination of the analogue parts with any switching or digital noise. Reproduced by arrangement with SILICON CHIP magazine 2021. www.siliconchip.com.au Practical Electronics | October | 2021