Circuit Surgery
Regular clinic by Ian Bell
Electronically controlled resistance – Part 2
L
ast month, in Part 1, westarted
looking at electronically controlled
resistance. This was prompted by
a question from user Kintaro posted to
the EEWeb forum. Two key approaches
to electronically controlled resistance are
a) to use transistors, particularly JFETs
(Junction Field Effect Transistors), as voltage-controlled resistors, and b) digital
potentiometer ICs, which are typically
controlled via a microcontroller over a
standard bus such as SPI or I2C. Part 1
discussed some specific points raised by
Kintaro, and we considered the properties of the JFET in relation to its use as a
voltage-controlled resistor. This month, in
Part 2, we will look in more detail at circuits using this technique – specifically use
of the JFET attenuator, which employs a
JFET as part of a potential divider circuit.
In Part 1, we explained how to use
LTspice to plot the characteristics of a
JFET, as shown in Fig.1. Similar plots
are often provided on device datasheets.
Fig.1 shows that we can divide the JFET’s
characteristics into two regions – saturation
Fig.1. LTspice plot showing regions of operation in JFET characteristics (ID vs VDS at
and ohmic. In the saturation region the JFET
various VGS). See previous month for simulation details.
acts like a constant-current source between
source and drain, with the current controlled by the gate-source
Implications of device characteristics
voltage. This is employed when the JFET is used as an amplifier.
Fig.2 shows the resistance is fairly constant over the plotted
The JFET’s ohmic region is characterised by resistive behaviour
drain-source voltage range of ±600mV and is better for lower
– increasing drain-source voltage (VDS) results in an increase
magnitudes of gate-source voltage. For both n and p-types, drainsource voltage can be of either polarity (Fig.2 covers both positive
in drain current (ID). The exact drain voltage-to-current relationship depends on the gate-source voltage. The slope
of the curves on Fig.1 are inversely proportional to
resistance, with the slope decreasing (higher resistance)
with increasing magnitude of gate-source voltage (VGS).
Unlike an ideal resistor, the drain-source resistance (rDS)
is not perfectly linear, however, if we look at relatively
small drain-source voltages (within the arc drawn near
the origin) the lines are relatively straight – it is this
part of the characteristic that can be used to implement
a good voltage-controlled resistor.
As discussed last month, and shown in Fig.2, we can
use LTspice to directly plot the drain-source resistance
variation with drain-source voltage at various gatesource voltages. This shows the JFET’s resistance
varies from about 130Ω to 390Ω as VGS is goes from
0V to −2V (at VDS = 0V). The plots in Fig.1 and Fig.2
are for an n-channel JFET, which requires a negative
gate-source (resistance control) voltage. p-channel
devices can also be used and require a positive gate- Fig.2. JFET drain-source resistance for various gate-source voltages for
drain-source voltages around zero (±600mV) – see also Fig.1.
source voltage.
Practical Electronics | October | 2022
41
Fig.6. LTspice schematic for a basic JFET attenuator
be reduced by feedback (see Fig.3), and we will look at
this again later.
Fig.3 shows the JFET’s resistance for a set of evenly
stepped gate-source voltages (0 to −2V in 0.25V steps). It
can be seen that the curves for each VGS value are not evenly
spaced. This shows that the control-voltage-to-resistance
relationship is also not linear. Variations in the gate-sourcevoltage-to-resistance relationship are likely to occur between
individual devices of the same type, so in some circuits the
ability to make adjustments (eg, using a trimmer potentiometer)
may be required.
Fig.3. JFET drain-source resistance for various gate-source voltages
for drain-source voltages around zero with feedback applied
(compare with Fig.2).
and negative VDS), which means we can have a zero-offset AC
signal across the voltage-controlled resistor. The JFET resistor
can operate with the ‘resistor’ voltage (VDS) down to zero – it
does not have a ‘turn-on’ voltage, or minimum VDS for operation.
The plot in Fig.2 is for a 2N3819 JFET – the values for
other devices will be different but follow a similar pattern.
The 2N3819 was not specially selected – it was the first in
LTspice’s list at the time of writing. The resistance range for
controlled
resistance
– Part 2
different JFETs may be significantlyElectronically
different (eg, up
to several
Voltage-controlled
attenuator
kilohms, rather than the hundreds of ohms seen in Fig.2). A
The most basic use of a JFET voltage-controlled resistor is
key device parameter is rDS(on), which is the minimum drainas a voltage-controlled attenuator in which the JFET forms
source resistance (at VGS = 0V) and depends on the physical
𝑟𝑟$%
structure of the device. A Vishay Siliconix datasheet for the
𝑣𝑣!"# = #
' 𝑣𝑣
𝑅𝑅
+ 𝑟𝑟$% '(
&
2N3819 sates a typical rDS(on) of 150Ω at a 1mA drain current
(implies VDS is 150mV), which is close to what we see in
part of a potential divider. The simplest form of this circuit
is shown in Fig.4. The output voltage is given by:
Fig.2. However, not all the various 2N3819 datasheets quote
𝑣𝑣!"#
The
this value directly. Using different JFETs from those specified
𝑟𝑟$%output
= 𝑅𝑅& # voltage can
' range from its lowest value when rDS =
𝑣𝑣
− 𝑣𝑣'(to very close to v if the JFET is switched
!"#
in a voltage-controlled resistance circuit, implies potentially
rDS(on) (at VGS = 0V),
in
different rDS(on) values, which means that other component
off by applying a large gate-source voltage. The maximum
output can be limited to less than vin by adding a resistor (R2)
values may need to be changed.
As mentioned last month, the fact that drain-source resistance
in parallel with the JFET, as shown in Fig.5. The output voltage
is non-linear (varies with drain-source voltage) means that
can be found by substituting the parallel combination of R2 and
circuits using JFET voltage-controlled resistors will introduce
rDS for rDS in the equation above. We briefly discussed parallel
signal distortion. A key implication of this is that when
combinations of voltage-controlled and fixed resistors last month.
we use the JFET as a voltage-controlled resistor, the signal
If R2 in Fig.5 is very large compared with R1 then the maximum
voltage across it must be small – in the range of tens to low
output will still be effectively equal to vin, but the output
hundreds of millivolts. This means signals may need to be
will not be an open circuit if the JFET is off (with the input
attenuated and amplified after being controlled by the JFET.
disconnected or very high impedance). This may be needed in
Smaller signal voltages across the JFET reduce distortion, but
some applications if an open circuit is not a desirable condition
also risk decreasing (ie, worsening) the signal-to-noise ratio.
for whatever is connected to the output of the attenuator.
As we showed last month, the resistance non-linearity can
Attenuator simulation
Input
Input
R1
R1
Output
J1
R1
Output
Output
J2
rDS
Control
a)
Input
Control
b)
Fig.4. (left) (a) Basic JFET attenuator (b) Potential divider equivalent circuit.
Fig.5. (right) JFET attenuator with series resistor.
42
R2
Fig.6 shows an LTspice schematic for investigating
the basic JFET attenuator. The input signal is a
1kHz sinewave, and the control voltage is ramped
from 0V to −3.5V over 50ms using a PWL (piecewise
linear) source. The following SPICE directives:
.option plotwinsize=0
.options numdgt=7
.four 1kHz 10 V(out)
together with the 10ns minimum time step in
the transient simulation command are included
to facilitate distortion analysis. Performing FFT
(fast Fourier transform) and distortion analysis
in LTspice was discussed in the July 2022 issue,
Practical Electronics | October | 2022
Fig.7. Results from LTspice JFET
attenuator circuit in Fig.6.
so we will not repeat the details here. If
this analysis is not required, the time step
can be increased and the three directives
removed to save time and file space.
The results of simulating the circuit
in Fig.6 are shown in Fig.7. The input
is a constant 200mV peak sinewave,
and output follows this waveform at an
amplitude set by the control voltage.
Unlike the control voltage ramp, the
envelope of the output amplitude is
not a straight line – the control voltage
to output amplitude is not a linear
relationship. The output reaches its
maximum value (equal to the 200mV
input level) for control voltages beyond
about −3.2 V, but note the waveform is
not symmetrical, particularly at larger
amplitudes, above about 100mV. This is
due to the nonlinear resistance which
does not vary symmetrically about zero
drain-source voltage (see Fig.2). For
low control voltages there is relatively
little variation in output voltage with
control voltage, so a more limited
control voltage range than 0 to −3.5V
may be better in practice than the full
Electronically controlled resistance – Part 2
range shown here.
The minimum output signal, when the
control voltage is zero, is about 23mV
(this can be measured
by zooming in on
𝑟𝑟$%
𝑣𝑣!"# = part
#
' 𝑣𝑣'( and using the
the initial
of V(out)
𝑅𝑅 + 𝑟𝑟$%
cursors). By &rearranging
the potential
divider equation as follows:
Fig.8. Distortion on the output from the JFET attenuator.
𝑣𝑣!"#
𝑟𝑟$% = 𝑅𝑅& #
'
𝑣𝑣!"# − 𝑣𝑣'(
we can find rDS at this point as 1000 ×
23/(200 − 23) = 130Ω, which matches with the value for VGS
= 0 in Fig.2.
Distortion
Fig.9. LTspice schematic for a JFET attenuator with feedback.
Although the amplitude envelope (peaks of V(out), shown
in the bottom pane) looks asymmetrical in Fig.7, distortion
is not particularly visible to the eye when zooming in on the
sinusoidal waveform. If we increase the input to 1V it is more
clearly seen – see Fig.8. The LTspice harmonic distortion
analysis reports 10% THD for this signal (View > SPICE Error
Log from the menu). The simulation was run with the control
voltage V2 source changed to a fixed DC value of −3.2 V rather
than the PWL ramp setup in Fig.6.
As mentioned last month, distortion can be reduced by
feeding back 50% of the drain-source voltage to the gate.
This is achieved using a pair of resistors which form a
potential divider. The resistors used for
the feedback must be large to prevent
loading. Since the gate has a very high
effective input resistance, a feedback
network using large resistors will not
itself be loaded by the gate. Applying the
feedback to the circuit in Fig.6 results
Fig.10. Output from the JFET attenuator
with feedback (circuit in Fig.9). Distortion is
reduced compared with that seen in Fig.8.
Practical Electronics | October | 2022
43
in the circuit in Fig.9 (this
is configured with a fixed
rather than ramped control
voltage, but this is easily
changed). To achieve the
same output level as shown
in Fig.8 the control voltage
was doubled to −6.4 V, the
potential divider formed by
R2 and R3 halves the control
voltage as well as providing
feedback of 50% of the VDS
signal. The output, under
similar conditions to those
for Fig.8, is shown in Fig.10
– distortion is far less visible
and calculated by LTspice
to be 2.7%.
We c a n a l s o r u n t h e
control voltage ramp for
this circuit, changing V1
back to 200mV and using a
final control voltage of −7V
to account for the dividing
effect of the feedback
Fig.11. Results from Fig.9 with a 200mV input and 0 to −7V control voltage ramp.
resistors (V2 is set to PWL(0
0 50m -7) ). The results are shown in Fig.11. The
output amplitude range is the same as seen in Fig.7,
but the envelope is more symmetrical.
Feedback
Fig.12. JFET attenuator with capacitively coupled feedback.
Fig.13. Simulation results for the circuit in Fig.12.
44
Only the signal itself needs to be fed back in order to reduce
distortion (not any of the DC level on the drain). This
can be achieved by capacitively coupling the feedback,
as shown in Fig.12. The coupling capacitor and large
feedback resistance have a long time constant. For the
circuit in Fig.12, with R = 2MΩ and C = 10nF, the time
constant RC = 20ms, so the capacitor will take around
100ms (5RC) to fully respond to relatively fast changes
in the control voltage. The control voltage in the circuit
in Fig.12 is configured like that in Fig.6 – it ramps to
−3.5V. The doubled voltage
used in the circuit in Fig.9 is
not required because the DC
is blocked by the capacitor
in the feedback, so there is
no divider effect with respect
to the DC or slowly changing
control voltage.
The results from
simulating the circuit in
Fig.12 are shown in Fig.13.
The actual attenuation
control signal is the voltage
at the JFET gate – this is
shown as the magenta trace
on the upper plot pane. The
feedback signal can be seen
on top of the DC gate voltage.
The DC voltage change
on the gate lags behind
the input control voltage,
and, as noted above, takes
around 100ms to reach the
final control voltage level.
The shape of the amplitude
envelope in the lower pane
is different from that in Fig.7
and Fig.11 in the first 50ms
Practical Electronics | October | 2022
(time range in Fig.7 and Fig.11) because the gate
voltage no longer exactly follows the control
voltage. Compared with Fig.7, the feedback reduces
the asymmetry (as also seen in Fig.11).
If a step change is applied to the control voltage
the gate voltage will step by half the control step
and then follow the capacitor charging curve. The
slow response of the circuit to control voltage
changes may be a problem in some applications.
Fast changes in control voltages may also couple
to the output.
Input
C2
100nF
R6
V+
+
–
R1
R2
–
C1
10nF
V–
Control
V+
+
U1
Output
U2
V–
R3
J2
R4
R5
Adding op amps
JFET attenuators are commonly used in conjunction
with op amp amplifiers to buffer the output and Fig.14. Example voltage-controlled amplifier based on a JFET attenuator.
provide gain and possibly
buffer the input as well. An
example is shown in Fig.14.
This has a unity buffer using
U1 on the input – which is
useful here as the combined
impedance of R 1 and the
JFET is quite low and might
load the source connected
to the input. The output
from the JFET attenuator
is amplified by a noninverting op amp amplifier
(using U2) with a gain of
10 (= 1 + 9k/1k). When
the control voltage is at or
beyond −3.2 V the full input
is passed to the output, so Fig.15. using the op amp’s output for the JFET attenuator feedback signal.
the maximum gain of the
whole circuit is 10. The
maximum attenuation
occurs at minimum r DS ,
which in this case was
found in our discussion
above to be 130Ω, giving
an attenuation of 130/(1000
+ 130) = 0.115 (using the
potential divider formula).
The minimum gain of the
whole circuit is therefore:
0.115 × 10 = 1.15
If we add an amplifier
to the output of the JFET
attenuator, then we can
use the op amp’s output as
the source of the feedback
signal to reduce the
distortion. The op amp’s
low output impedance
means that we can use
smaller resistor values,
which reduce the time
Fig.16. Simulation results from the circuit in Fig.15.
constant of the feedback
circuit, and reduce control voltage
gate voltage tracks the control voltage
amp in this circuit has to be 0.05 of its
coupling to the FET drain as there is
ramp, unlike in Fig.13.
output. The potential divider formed
no longer a connection there via the
by R 2 and R 3 needs to be confi gured
feedback network. Fig.15 shows an
to attenuate the output by this factor.
Simulation files
LTspice schematic based on Fig.14,
For the values used, we have 5.26k/
Most, but not every month, LTSpice
with the feedback supplied from the
(100k + 5.26k) = 0.4997, which is very
is used to support descriptions and
op amp’s output. We need to feed back
close. The feedback needs to be as
analysis in Circuit Surgery.
50% of the drain signal, but this has
close to 50% as possible to minimise
The
examples
and files are available
been amplified by ten at the op amp’s
distortion. Simulation results are shown
for download from the PE website.
output, so the feedback from the op
in Fig.16, where it can be seen that the
Practical Electronics | October | 2022
45
