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KickStart by Mike Tooley Part 14: Legacy logic revisited Our occasional KickStart series aims to show readers how to use readily available low-cost components and devices to solve a wide range of common problems in the shortest possible time. Each of the examples and projects can be completed in no more than a couple of hours using ‘off-the-shelf’ parts. As well as briefly explaining the underlying principles and technology used, the series will provide you with a variety of representative solutions and examples along with just enough information to be able to adapt and extend them for their own use. This instalment explains how the use of ‘legacy logic’ can provide you with a simple and cost-effective solution to a variety of everyday circuit design problems. We follow the stages in the design process as the author delves deep into his ‘junk’ component store and shows how a simple Quiz Machine circuit can be constructed at a small fraction of the cost and complexity associated with one of today’s most popular microcontrollers. 1 input always results in a logic 1 output, and a logic 0 input always results in a logic 0 output. Buffers are normally used to provide extra current drive at the output but can also be used to regularise the logic levels present at an interface. Its triangular symbol shape is deliberate – think of it as a digital unity-gain amplifer. Fig.14.1. The original design concept for the Quiz Machine. W hen recently tasked with Inverter Inverters are used to ‘complement’ the logical state. In other words, a logic 1 input results in a logic 0 output, and vice versa. Just like buffers, inverters also Why legacy logic? The first issue was the cost. Even without the LCD display this project was going to be expensive and was likely to exceed my original budget by a factor of three. I needed a much simpler low-tech solution, so maybe I shouldn’t be using a microcontroller at all. In the end, and after a few ‘sleepless nights’ I eventually decided on a solution based on a single logic chip that can be purchased for less than 50p and which needs no coding at all! had been classified as ‘worth keeping’ (just in case I needed to carry out a repair on some elderly item of equipment) as well as a copious supply of computer panels stuffed with 14, 16 and 18-pin dual-in-line chips. This, then, was going to be my starting point: a quantity of TTL-compatible CMOS devices that had been used in constructional projects of a few decades ago. The symbols for some basic logic elements are shown, together with their truth tables in Fig.14.2. Note that, while inverters and buffers each have only one input, exclusive-OR gates have two inputs and the other basic gates (AND, OR, NAND and NOR) are commonly available with up to eight inputs. The action of each of the basic logic gates can be summarised as follows: Revisiting the basic elements of logic Resorting to my extensive ‘junk’ component store I discovered a host of logic chips that Buffer Buffers do not affect the logical Fig.14.2. Symbols for basic logic elements, together state of a digital signal – a logic with their truth tables. designing a simple Quiz Machine I immediately settled on my usual ‘go to’ solution. An Arduino Uno, together with an LCD display and a few other components should do the job nicely. A prototype was duly assembled and with the addition of a few dozen lines of code it all worked well. Later, and having moved on from the prototype stage with a first iteration of the PCB in front of me, I began to have a few nagging doubts about this solution. Practical Electronics | December | 2023 61 logic 1. Any other input combination will produce a logic 1 output. A NAND gate, therefore, is nothing more than an AND gate with its output inverted, or put another way, an AND gate followed by an inverter. The circle at the output denotes this inversion. Fig.14.3. Symbols for monostable and bistable elements. NOR Likewise, a NOR gate (‘not-OR’) will only produce a logic 1 output when all inputs are simultaneously at logic 0. Any other input combination will produce a logic 0 output. A NOR gate, therefore, is simply an OR gate with its output inverted, or an OR gate followed by an inverter. Again, a circle is used to indicate inversion. XOR The exclusive-OR (XOR) gate produces a logic 1 output whenever either one of inputs is at logic 1 providing the other input is at logic 0 – they only ever have two inputs. Exclusive-OR gates produce a logic 0 output whenever both inputs have the same logical state (ie, when both are at logic 0 or both are at logic 1). Fig.14.4. Using cross-coupled NAND and NOR logic gates to realise an R-S bistable. provide extra current drive and are used in interfacing applications, where they provide a means of regularising logic levels present at the input or output of a digital system. The circle indicates inversion. AND The output of an AND gate will only produce a logic 1 output when all inputs are simultaneously at logic 1. Any other input combination results in a logic 0 output. OR An OR gate will produce a logic 1 output whenever any one or more inputs are at logic 1. Putting this another way, an OR gate will only produce a logic 0 output when all of its inputs are simultaneously at logic 0. NAND A NAND gate (‘notAND’) will only produce a logic 0 output when all inputs are simultaneously at Monostable and bistable elements A logic device which has only one stable output state is known as a monostable. The output of such a device is initially at logic 0 (low) until an appropriate level change occurs at its trigger input. This level change can be from 0 to 1 (called ‘positive-edge trigger’) or 1 to 0 (called ‘negative-edge trigger’) depending upon the particular device or configuration. Upon receipt of a valid trigger pulse the output of the monostable changes state to logic 1. Then, after a time interval determined by external RC-timing components (a resistor and capacitor), the output reverts to logic 0. The device then stays at logical 0 output until the arrival of the next trigger. A typical application for a monostable device is in stretching a short duration pulse. By contrast, the output of a bistable has two stable states (logic 0 or logic 1) and, once set the output of the device will remain at a particular logic level for an indefinite period until reset. A bistable thus constitutes a simple form of memory because it will remain in its latched state (whether ‘set’ or ‘reset’) until commanded to change its state (or until the supply is disconnected). Various forms of bistable are available including R-S, D-type and J-K-types (see Fig.14.3). R-S bistables The R-S bistable is the most basic form of bistable. The device has two inputs, SET and RESET, and complementary outputs, Q and Q (the inverse of Q). A logic 1 applied to the SET input will cause the Q output to become (or remain at) logic 1, while a logic 1 applied to the RESET input will cause the Q output to become (or remain at) logic 0. In either case, the bistable will remain in its SET or RESET state until an input is applied in such a sense as to change it. R-S bistables can be easily implemented using crosscoupled NAND or NOR gates, as shown in Fig.14.4. These arrangements are, however, unreliable as the output state is indeterminate when both the SET and RESET inputs are simultaneously at logic 1. D-type bistables The D-type bistable has two principal inputs: D (standing variously for ‘data’ or ‘delay’) and CLOCK (written as CK or CLK). The data input (logic 0 or logic 1) is clocked into the bistable such that the output state only changes when the clock changes state (see Fig.14.5). Operation is thus said to be synchronous. Additional subsidiary inputs (which are invariably active low) are provided which can be used to directly set or reset the bistable. These are usually called PRESET (PR) and CLEAR (CLR). D-type bistable elements can be used both as ‘latches’ (a simple form of memory) and as binary dividers. J-K bistables J-K bistables are the most sophisticated and flexible of the bistable types and they can be configured in various ways, including binary dividers, shift registers, and latches. J-K bistables have two clocked inputs (J and K), two direct inputs (PRESET and CLEAR), a CLOCK (CK) input, and outputs (Q and Q). As with R-S bistables, the two outputs are complementary (ie, when one is 0 the other is 1, and vice versa). Similarly, the PRESET and CLEAR inputs are invariably both active low (ie, a 0 on the PRESET input will set the Q output to 1 whereas a 0 on the CLEAR input will set the Q output to 0). Fig.14.5. (right) Clocking a D-type bistable element to change its output state. Logic families Digital integrated circuit devices are often classified according to the semiconductor technology used in their fabrication. The logic ‘family’ to which a device belongs being largely instrumental in determining its operational characteristics (such as power consumption, speed, and immunity 62 Practical Electronics | December | 2023 Table 14.1 HC-logic family characteristics Fig.14.6. Standard logic levels for HC-series logic devices. to noise). The two most important legacy logic families are CMOS (Complementary Metal-Oxide Semiconductor) and TTL (Transistor-Transistor Logic). Over the past 50 years each of these families has been extended and further sub-divided. The most appropriate logic family for use in our Quiz Machine uses highspeed CMOS technology. This ‘HCfamily’ of devices combines several of the desirable characteristics of CMOS technology with traditionally faster and more robust TTL logic. Logic levels Logic levels are simply the range of voltages used to represent the logic states 0 and 1. The logic levels for HC-family devices are similar to those used by standard CMOS logic and differ from those associated with conventional TTL and LS-TTL devices. Fig.14.6 illustrates the usual range of voltage and corresponding logic levels used with HCfamily devices. There are a few important things to consider from Fig.14.6: 1. The minimum output high voltage (VOHmin) must be greater than the minimum input high voltage, VIHmin. 2.  The maximum output low voltage (V OLmax ) must be less than the maximum input low voltage, VILmax. 3. The circuit designer must take steps to ensure that the input high (VIH) and input low (VIL) voltages are well within the acceptable range. Failure to do this may well result in unpredictable performance. 4. The transition voltage (Vt) is nominally at 50% of the supply voltage, VCC. When the input logic levels change rapidly from 0 to 1 or 1 to 0 it is usually assumed that the change of output state occurs at this point. It is important to note that HC-devices are capable of operating at conventional TTL supply voltages (5V ± 10%) and also with the usual range of input levels used by standard TTL devices. They can thus be used as pin compatible TTL replacements to reduce power Practical Electronics | December | 2023 Symbol Parameter VCC Value Units Min Typ Max Supply voltage 2.0 5.0 6.0 V VI Input voltage range (note 1) 0 n/a VCC V VO Output voltage range (note 1) 0 n/a VCC V tr, tf Rise/fall time (note 2) 0 6.0 500 ns VIH Input high voltage (note 2) 3.5 4.8 5.0 V VIL Input low voltage (note 2) 0 0.2 1.5 V VOH Output high voltage (note 2) 4.5 4.9 5.0 V VOL Output low voltage (note 2) 0 0.1 0.5 V Notes 1. Must not be outside the quoted range 2. Values are quoted for a typical VCC of 5V Table 14.2 Common HC-logic family devices Device Logic function Package (DIL versions) 74HC00 Quad 2-input NAND 14-pin 74HC02 Quad 2-input NOR 14-pin 74HC04 Hex inverter 14-pin 74HC08 Quad 2-input AND 14-pin 74HC14 Hex Schmitt inverter 14-pin 74HC32 Quad 2-input OR 14-pin 74HC73 Dual J-K bistable (with preset and clear) 14-pin 74HC74 Dual D-type bistable (positive edge trigger) 14-pin 74HC123 Dual monostable (can be retriggered) 16-pin 74HC138 3-to-8-line decoder 16-pin 74HC164 8-bit serial input shift register 14-pin 74HC165 8-bit parallel input shift register 16-pin 74HC595 8-bit serial to parallel shift register 16-pin consumption without loss of speed. Some typical HC-family specifications are summarised in Table 14.1 and some common devices are listed in Table 14.2, together with their logic function. Unlike earlier CMOS and MOS devices, the inputs and outputs of HCseries devices are protected against electrostatic discharge that may occur in typical handling situations. That said, it is always wise to get into the habit of observing ESD precautions when handling or using these devices (see Going further). In some applications you might find that you don’t need to use all the logic elements provided within a particular IC package (eg, you might only need two of the four NOR gates within a 74HC02 package). If that’s the case, it’s important to follow manufacturers’ recommendation concerning unused inputs and outputs. Generally, this means that unused inputs should be tied to VCC while unused outputs are simply left floating. In addition, a capacitor of typically 100nF should be connected as close as possible between the VCC and GND pins of each logic device (ie, between pin-7 and pin-14 of a 74HC02). Failure to observe these precautions can sometimes result in unreliable operation, oscillation and instability. Design specification As with any electronic design project, it is important to start with a sufficiently detailed specification. Our Quiz Machine is to have two momentary action pushbuttons, one for each team. When either of the buttons is operated, an LED should light to identify the answering team. So that there’s no uncertainty as to which of the teams has answered first, the button for the other team must be ‘locked out’. Once the answer has been evaluated the quiz master can clear the state of the LEDs 63 Fig.14.9. Pin connections for the 74HC02 quad two-input NOR gate. supply and be small enough to fit into a small ABS enclosure. Memory From the design specification is should be obvious that the Quiz Machine needs to ‘remember’ that one or other of the TEAM buttons has been pressed. Once pressed, it should not be necessary to hold the pushbutton down continuously. Fig.14.7. Quiz Machine based on logic gates and J-K bistable elements. In a microcontroller application this can be achieved by reading the state of the two TEAM buttons and then setting or resetting variables accordingly. With the ‘legacy logic’ version this ‘memory feature’ can be realised by using the button status to set a bistable element. Note that we will need two bistable elements, one for each of the TEAM button inputs. We also need to ensure that once one of the two bistable elements has been SET the other bistable should no longer be able to react to a button press (thus ‘locking out’ the other team’s pushbutton). This can be achieved by using some simple logic, as shown in Fig.14.7. This arrangement can be realised using a total of three dual-in-line chips, a 74HC02, 74HC08 and 74HC73 (see Table 14.2). When working with logic circuits it is often possible to minimise a design and the arrangement shown in Fig.14.7 should just be considered a good starting point. If we replace the two J-K bistable elements with cross-coupled NOR gates we can reduce the device count by one. A further reduction can be made by using the two Q outputs to provide the logic HIGH state for the push-button inputs (instead of simply connecting the pushbuttons to the +5V supply). This minimised arrangement is shown in Fig.14.8 and it uses a single 74HC02 logic device (see also Fig.14.9). Simulation Before arriving at a breadboard layout, it is well worth checking the prototype design using a simulation package such as Tina or Deeds. This will allow you to assemble a ‘virtual circuit’ and check that it all works as intended. Figs.14.10 and 14.11 show how this can be done. Each of the inputs (SW1, SW2 and SW3) can be operated while observing the state of the two outputs (D1 and D2). It is also important to check that the RESET button (SW3) operates correctly and that the ‘lockout’ feature works as planned. Fig.14.8. Minimised version of the Quiz Machine logic using two pairs of cross-coupled, two-input NOR gates. using the RESET button before awaiting an answer to the ensuing question. We thus have three momentary-action pushbutton inputs which will be labelled ‘TEAM A’, ‘TEAM B’ and ‘RESET’. The outputs will be two large LED indicators which can later be augmented by external lamps and buzzers (if or when the need arises). The circuit is to operate from a low-voltage 5V 64 Breadboarding Having checked the circuit simulation (and before moving on to the final prototype stage) it can be useful to assemble the circuit on a breadboard using physical component parts, as shown in Fig.14.12. This may occasionally reveal differences between the behaviour of virtual component models and their physical counterparts. It will also provide you with a further opportunity to confirm your design before committing it to a stripboard or a (somewhat more expensive) printed circuit board layout. Note that coloured Practical Electronics | December | 2023 Fig.14.11. (right) Simulating an earlier version of the circuit using the Deeds digital logic environment. Fig.14.10. Simulating the circuit in Fig.14.8 using Tina Pro. Fig.14.12. Breadboard testing the circuit in Fig.14.8. Table 14.3 Going further with legacy logic Topic Source Notes Logic families Texas Instruments (TI) provides an excellent overview of the different families of logic. The Texas Instruments Logic Guide is available from: https://bit.ly/pe-dec23-ti HC-series logic The Toshiba HC-series application note provides useful information and detailed technical specifications. HC-series logic chips can be obtained from most electronic component suppliers. The Toshiba application note is available from: https://bit.ly/pe-dec23-tosh Deeds simulation software Conceived as a common resource for working in digital electronics, the Deeds environment is an excellent learning resource that allows you to quickly and easily build, test and refine your digital logic circuits The Deeds simulation package can be freely downloaded from: https://bit.ly/pe-dec23-deeds A special Texas Instruments version of the software, Tina-TI, can be downloaded for free from: https://bit.ly/pe-dec23-tinati Tina simulation software The powerful and intuitive Tina Design Suite from DesignSoft can help you simulate a vast range of analogue and digital circuits. Logic circuits For those with no previous experience, Part 4 of Electronics Teach-in 4 (from Electron Publishing) provides a basic introduction to logic circuits. It also shows how the popular Circuit Wizard software can be used to simulate and test practical logic designs Available (as part of a Teach-in bundle) from Electron Publishing at: https://bit. ly/pe-dec23-eti345 Logic circuits and simulation techniques The author’s own book, Electronic Circuits: Fundamentals and Applications (Fifth Edition 2020 published by Routledge 9780367421984) includes a general introduction to logic circuits and simulation techniques. Available from Electron Publishing at: https://bit.ly/pe-dec23-mtoo Practical Electronics | December | 2023 The Student and Full/Hobbyist versions of Tina Design Suite can be purchased from the PE website. Budget versions of the software available are available for students and hobbyists respectively at: https://bit.ly/pe-dec23-tinastud https://bit.ly/pe-dec23-tinahob 65 Fig.14.13. Stripboard prototype layout for the circuit in Fig.14.8. (Not shown, but important: track cuts C-I 12 between IC pins.) Fig.14.14. The completed prototype ready for testing. interconnecting wires will help reduce some of the potential confusion when it comes to the wiring arrangement of a large breadboard circuit. Prototype The prototype layout for the Quiz Machine is shown in Fig.14.13. This uses a small piece of stripboard (17 strips by 24 holes). Note that all the tracks beneath IC1 must be broken (not shown in Fig.14.13). The completed prototype (ready for testing) is shown in Fig.14.14. Finally, to provide you with some extra ‘food for thought’, Fig.14.15 provides some circuit fragments from the author’s recent use of ‘legacy logic’. So, if you have a simple application it could be that ‘legacy logic’ will provide you with an easy and inexpensive solution without having to resort to a complex and expensive microcontroller design! Going further This section details a variety of sources that will help you locate the component parts and further information that will allow you to make and use legacy logic in your own applications. It also provides some useful links that will help you get up to speed with the necessary underpinning knowledge for the key topics discussed. Fig.14.15. Some useful circuit arrangements based on ‘legacy logic’. 66 Practical Electronics | December | 2023