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Circuit Surgery Regular clinic by Ian Bell Topics in digital signal processing – ADCs W e are looking at various topics related to digital signal processing (DSP). DSP covers a wide range of electronics applications where signals are manipulated, analysed, generated, stored or displayed as digital data, but originate from, and/or are output as, real-world signals for interaction with humans or other parts of the physical world. Fig.1 shows the key elements of a generic DSP system with a signal path from an analogue input via digital processing to an analogue output. This does not necessarily represent every DSP system (not all have all the parts shown) but it serves as a reference for the various subsystems we will look at. Last month we looked at sampling. We have not discussed all the details of input filtering and the sampling process yet, but at this point it is useful to look further down the signal path to the analogueto-digital converter (ADC) due to its fundamental role in the digitisation of analogue signals. Quantisation In a similar way to the finite time step limitation discussed last month, there is also a finite limit on the number of different values a digitised signal can take. This shift from a very large (or effectively infinite) set of possible signal values to a smaller one is called ‘quantisation’. It is similar to the rounding of values in numerical calculations. Digital hardware (and the software running on it) can handle numerical calculations which have a very large number of possible values. The level of numerical detail used is referred to as the precision (eg, how many decimal digits a number can represent). Increasing precision requires more hardware and/or more processing time (or more speed to process a given amount of data in a given time). Analogue In Antialiasing filter Sample and hold Digital hardware and software considerations may limit the number of possible values per sample that is practical in a given DSP system, but the limit (at the point the signal is digitised) is more likely to be determined by the choice of ADC (availability and affordability in the context of a particular design). ADCs input an analogue signal and typically the output is a digital numerical value as a binary integer (whole number value). The number of possible values in a digitised signal is determined by the number of bits (binary digits) in the ADC’s output. Specifically, for an N-bit output there are 2N possible values. For example, for 10-bits there are 210 = 1024 possible values. Increasing the number of bits increases the demands on the analogue circuitry in the ADC. The more bits the smaller the input differences the ADC has to discriminate to correctly convert it to the digital code. Imperfections, errors and noise in the circuitry will reduce the obtainable precision, so more bits require better design and technology, and also generally leads to slower sampling rates. Single ended Analogue input signal Analogue input signal Reconstruction filter Conv Conversion start code 0V Out ADC In– Conv Gnd In+ Fig.2. Generic schematic symbols for ADCs. is the maximum for a ‘standard’ ADC – the 32-bit devices use oversampling – they input samples at a much faster rate than they output them, which facilitates reduction of noise and improves effective resolution. Analog Devices’ ADCs have speeds ranging from around two samples per second to over 10 giga samples per second (GSPS). The extremes relate to devices aimed at specific purposes – high-precision sensing applications at the slow end, and the fastest for advanced RF signal processing systems such as satellite communications. The latter devices cost in the low thousands of pounds, but of course there are many inexpensive ADCs for more everyday projects. ADCs are often used with microcontrollers and are typically connected to the microcontroller via a standard serial bus such as SPI or I 2C. A few ADCs with parallel outputs are also available. As well as separate, standalone ADC ICs there are often ADCs built into microcontroller devices. These generally have moderate capabilities but are suitable for many projects and help reduce cost, complexity and component count. If a suitable microcontroller and on-chip combination is not available, then one of the many discrete ADCs mentioned above can be used. Analogue DAC Gnd Digital output code Out 0V There are a large number of ADC integrated circuits on the market, so there is plenty of choice and variety. To find a device to suit your needs, as with other ICs, you can visit the website of IC manufacturers (for example, Analogue Devices at www.analog.com and Texas Instruments at www.ti.com) or component distributors (like Farnell and RS) where you can find selection tables which you can sort according to device parameters (such as number of bits and maximum sampling rate) as well as finding price and availability information. Analog Devices is a leading manufacturer of data converters. At the time of writing they provide ADCs ranging from 6 bits up to 32 bits. Generally, 24-bits Digital processing In ADC Differential Choosing ADCs Digital ADC Reference(s) and Supplies reference selection Out ADC connections and signals Fig.1. Generic DSP system structure. Fig.2 shows generic schematic symbols for an ADC – not all the signals shown may be actual pins Practical Electronics | June | 2024 63 Code output Code output 111 2N – 1 110 101 100 011 010 001 000 0 1 a) 2 3 4 5 Input: Vin/LSB 6 7 c) Input: Vin/LSB 2N – 1 Code output 1111 An ADC’s output is a digital code which may be directly available, or via a serial interface. Bipolar ADCs must output binary values in a signed number format, typically 2s-complement format is used, but consult device datasheets to be sure of the details. Something is required to control the start of the conversion process (the point in time when a sample is taken). This could be a done via a specific input pin, an on-chip timer/oscillator, or a command sent over a serial interface. On microcontrollers, programmable on-chip timers are often used to control sample timing of on-chip ADCs. 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 Supplies and references 0011 In order to accurately convert a specific absolute voltage to a specific code the ADC requires an accurate reference voltage. This may be the supply, but supplies are often subject to variation and may also be noisy. Therefore, it is common to use voltage reference circuits instead of the supply. These output very accurate fixed voltages, which change very little with temperature and over time. Some ADCs allow a choice of reference source (eg, supply, on-chip reference, or external reference via device pins). Using the supply as a reference works best if the value converted is effectively a ratio of the supply (eg, via a resistive sensor in a potential divider) because supply shifts have the same relative effect on the ADC and measured value, so the effect of supply shifts cancels out. ADCs may have a simple single supply pin, or there may be multiple supplies. This might include positive and negative supplies for bipolar devices and separate supply pins for the analogue and digital parts of the chip. The latter may be due to different operating voltages, but using separate supplies also helps prevent noise from digital switching disturbing the analogue circuitry. 0010 0001 0000 0 1 2 3 b) 4 5 6 7 8 9 10 11 12 13 14 15 Input: Vin/LSB Fig.3. Input-output (transfer) function for ADCs (a) 3-bit ADC (8 output codes), (b) 4-bit ADC (16 output codes), (c) ADC with a (near) infinite number of bits, N – this is the ideal ‘straight-line’ transfer function. – the functionality can be obtained via commands over a serial bus. ADCs may have one or two inputs for the signal being converted. One input is referred to as ‘single ended’ and two as ‘differential’. For single-ended inputs the value converted is the input voltage with respect to ground, and for differential it is the voltage difference between the two inputs (Vin+ – Vin–) which is converted. Single-ended circuits are simpler but differential inputs provide the ability to reject (cancel out) signals which are common to both inputs (common-mode rejection). Some ADCs have differential inputs which have a restricted range of voltages on one of the inputs, typically tens or hundreds of millivolts with respect to ground. These are called pseudodifferential inputs. One of the ‘pseudo-differential’ inputs is effectively ground but the differential nature of the inputs still provides common-mode rejection. Fully differential ADCs allow a wider range of voltages on both inputs. ADC inputs (both single ended and differential) may be either unipolar or bipolar. Unipolar inputs only allow voltages of one polarity (typically positive with respect to ground), whereas bipolar inputs can be positive or negative. 64 ADC transfer functions and LSB Fig.3 shows the input-output relationship for three data converters. In all cases the input is an analogue voltage, and the output is a digital code. An ADC transfer characteristic has a staircase shape. The more bits in the output code the more steps we get in the complete transfer characteristic, as can be seen by comparing the 3- and 4-bit characteristics in Fig.3a and Fig.3b. If we had a (near) infinite number of bits in the output code the transfer characteristic would be a perfect straight line as seen in Fig.3c. As indicated above, the range of analogue input voltages over which an ADC performs conversion (the full-scale range Practical Electronics | June | 2024 Code output Ideal straight line transfer function Quantisation error 1.5 LSB +0.5 LSB 111 Input: Vin/LSB 110 101 –0.5 LSB 0 100 0.5 LSB Width of one step is 1 LSB 001 000 2 3 4 5 6 7 Fig.5. Difference between the ideal straight-line transfer function and the actual transfer function of a perfect 3-bit ADC. The difference is the quantisation error. 011 010 1 0 VRefL 1 2 3 4 5 Input: Vin/LSB 6 7 8 VRefH Full-scale range (FSR) Fig.4. Details of a unipolar mid-tread ADC transfer function. – FSR) is set by two reference voltages in the ADC circuit – the low reference voltage (VRefL) and the high reference voltage (VRefH ), see Fig.4. Often the low reference is ground, but it does essing Topics – ADCs ing Topics – ADCs not have to be. An N-bit ADC converts analogue input data into 2N codes. The voltage difference between adjacent codes is called the ‘least-significant bit’ (LSB), which is given by: (𝑉𝑉RefH 𝑉𝑉RefL (𝑉𝑉RefH ) ) − 𝑉𝑉−RefL 𝐿𝐿𝐿𝐿𝐿𝐿 𝐿𝐿𝐿𝐿𝐿𝐿 == & 2 & 2 For example, if a 12-bit ADC has VRefL = 0 and VRefH = 5V then the LSB is given by: 5 5 5 5 = 1.22mV LSB LSB = =12 2=12 = 4096 = 1.22mV 2 4096 The transfer functions shown in Fig.3 and Fig.4 have the first transition 0.5 LSB above the bottom end of the FSR and the final transition 1.5 LSB below the top of the FSR. This is a common approach and is referred to as a ‘mid-tread’ transfer function because the point in the middle of the FSR at (VRefL – VRefH)/2 (input = 4 in Fig.4) coincides with a flat part of staircase (the tread if it were a real staircase). Shifting the transfer function 0.5 LSB results in a mid-riser transfer function, which has a code transition at the middle of the FSR. ADC datasheets often have diagrams like Fig.4 which explain the device’s specific transfer function. You may see the LSB defined as: range/(2N – 1), which may be valid for some transfer functions. Quantisation errors Due to the finite number of codes, the voltage represented by the ADC’s code after conversion will not generally be exactly equal to the original input voltage. The difference is known as the ‘quantisation error’. This error has a maximum value of ±0.5 LSB with the transfer functions illustrated here. The variation of error with input voltage for a 3-bit ADC is shown in Fig.5 (for the transfer function in Fig.4). Quantisation error is not the result of non-ideal circuit components; it is a fundamental property of the conversion process. Real ADCs will produce additional errors: offset error, zero-scale error, full-scale error, gain error, differential non-linearity (DNL) and integral nonlinearity (INL). We will discuss these shortly. If an ideal ADC is used to measure the same fixed voltage in a noise-free circuit the same quantisation error will occur each time. However, if an ADC is used to sample a continuous Practical Electronics | June | 2024 signal (eg, audio) then the quantisation errors will be different on each conversion and over time they will have the same statistical properties as random errors. Thus, quantisation adds random noise to a digital representation of a (changing) signal which was not present in the original analogue input. For N-bit quantisation the signal-to-noise ratio, (SNR) of the quantised signal is given by: SNR = 6.02×N + 1.76 dB Adding an extra 1 bit of resolution provides about 6dB improvement in the SNR. This is for an ideal converter; real converters will add additional noise. Thinking about the size of an LSB is useful when designing a system containing ADCs. The resolution used should be commensurate with the accuracy and SNR requirements of the system. Too low and the ADC may be the weakest link, but if it is much higher than necessary you may be wasting your money. Table 1 helps provide an idea of the size of 1 LSB by expressing it as a percentage or parts per million of full input range and as a voltage for an ADC with a 5V range. The SNR due to the quantisation error is also given. Offset and gain errors Zero-scale error is the difference between the actual and ideal transition voltage to the first code, as shown in the example in Fig.6 where the error is about +1.75 LSB. As with many ADC characteristics, this error is usually expressed in terms of LSBs rather than absolute voltage values since this is better for making comparisons between ADCs. ADCs may have a constant DC offset error – a fixed DC error across the entire conversion range. If there are no other sources of error then the offset error and zero-scale error will be the same (as in Fig.6). However, in general this is not guaranteed. In Fig.4 we saw a comparison between the ideal straight line transfer function and the actual step by step function of Table 1 – properties of ideal ADCs related to numbers of bits (ppm is parts per million). Number of bits Number of Codes Relative size of LSB SNR in dB LSB voltage for 5V input range 3 8 13% −20 625mV 4 16 6.3% −26 313mV 8 256 0.39% −50 19.5mV 10 1024 980 ppm −62 4.88mV 12 4096 240 ppm −74 1.22mV 16 65536 14 ppm −98 76.3μV 22 4194304 0.24 ppm −134 1.19μV 24 16777216 0.060 ppm −146 0.298μV 65 Code output Code output Ideal transfer function 111 111 110 110 101 101 100 100 011 011 010 010 001 001 000 0 VRefL 1 2 3 Offset error and zero-scale error 4 5 Transfer function with offset error 6 7 Input: Vin/LSB 000 VRefH 0 VRefL Transfer function with gain error 1 2 3 Full scale error 4 5 Ideal transfer function Fig.6. Example of ADC zero-scale and offset errors. Fig.7. ADC full-scale and gain errors. a perfect ADC with a limited number of bits. Fig.7 shows an ADC in which the slope of this ideal line, as extrapolated from the staircase, is different from what it should be; that is, the ADC has a gain error. An effect of gain error is that the input voltage at which the transition to the largest output code will be wrong, as shown in Fig.7. The full-scale error of an ADC is the difference between the actual and ideal final code transition voltage. The ADC transfer function in Fig.6 only has full-scale error, but a real device may have a zero-scale error as well. If an ADC has no nonlinearities and no zero-scale error, or if the offset is removed by shifting the transfer function accordingly, the resulting full-scale error will be related to only the error in gain (slope of the ideal transfer function). Thus gain error for an ADC can be defined as Monotonicity and missing codes Gain Error = Full Scale Error – Zero Scale Error Like offset error, this definition may be problematic if the ADC has significant nonlinearities around the final transition voltage. Code output Code 011 is missing. Output jumps straight from 010 to 100. 111 110 100 011 010 001 0 VRefL 1 2 3 4 5 Input: Vin/LSB 6 Fig.8. ADC transfer function with a missing code. 66 7 VRefH The errors we have considered so far (offset and full scale) do not cause any deviation from a uniform ‘staircase’ which could be represented by an ideal straight line. In general, ADCs do not have such perfect straight-line transfer functions. Errors which cause deviations from this are called nonlinearities. Before looking at nonlinearities in general we will define a couple of special cases, which represent relatively large anomalies in the transfer function. Fig.8 shows an ADC transfer function with a missing code. A missing code means that the ADC never outputs some digital code values, whatever input is applied. This looks very dramatic in Fig.5 but would seem less so with more bits. If your design uses an ADC with a few more bits than you really need then missing codes will probably not be a problem. ADCs may be guaranteed to have no missing codes – this will usually be stated on the datasheet. Ideally, increasing the input voltage to an ADC will either not change the output code or produce a higher code value. If increasing the input voltage produces a lower code value at any point over the ADC’s input range then the converter is said to be ‘non-monotonic’. This is illustrated in Fig.9. ADC datasheets will usually state if a device is guaranteed to be monotonic. Monotonicity is particularly important if the ADC is part of a feedback loop since non-monotonicity can lead to instability of the loop (oscillations). Linearity 101 000 6 Input: Vin/LSB 7 VRefH Two key parameters for characterising the quality of an ADC’s transfer function are differential non-linearity (DNL) and integral non-linearity (INL). These indicate how much the transfer function deviates from a straight line. DNL measures the difference between the ideal and actual code widths. The code width is the range of voltage for which a particular code is output by the ADC – it is the width of each ‘tread’ in the staircase transfer function. Ideally, the code width is 1 LSB, which corresponds with a DNL of 0. Other code widths have non-zero DNLs, for example, if the code with is 1.5 LSB the DNL is +0.5. DNL and INL are illustrated in Fig.10 which shows an ADC transfer function with significant nonlinearity. INL measures the accumulation of error as one moves through the converter’s codes (the sum of INL’s from the first code to the current code). A Practical Electronics | June | 2024 Code output Code output 111 111 110 110 101 101 100 100 011 011 010 010 001 001 000 0 VRefL 1.5 LSB DNL = +0.25 DNL = +0.5 DNL = 0 DNL = 0 DNL = –0.25 1 2 3 4 5 Input: Vin/LSB 6 7 DNL = –0.5 000 VRefH 0 VRefL 1 2 3 Actual transfer function is not a straight line. Bit 1 2 3 4 DNL in LSB –0.5 –0.25 0 0 4 5 Ideal straight line transfer function INL in LSB –0.5 –0.75 –0.75 –0.75 6 7 Input: Vin/LSB 8 VRefH Fig.9. Non-monotonic ADC transfer function. Fig.10. Nonlinear ADC transfer function showing DNL and INL values. missing code has a DNL of −1.0. The transfer function in Fig.10 does not have any zero-scale or full-scale errors – these are usually corrected before DNL and INL are calculated to provide more meaningful linearity values. The maximum positive and negative DNL and INL values may be given on the datasheet. For more than a few bits it is not practical to list all values but graphs of DNL and INL against digital code may be provided. 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