Silicon ChipCircuit Surgery - October 2024 SILICON CHIP
  1. Contents
  2. Publisher's Letter: Updates on kits and the magazine
  3. Feature: Techno Talk - Sticking the landing by Max the Magnificent
  4. Feature: Net Work by Alan Winstanley
  5. Feature: The Fox Report by Barry Fox
  6. Project: 500W Monoblock Class-D Amplifier by Phil Prosser
  7. Subscriptions
  8. Feature: Circuit Surgery by Ian Bell
  9. Project: TQFP Programming Adaptors by Nicholas Vinen
  10. Feature: Audio Out by Jake Rothman
  11. Feature: Electronic Modules - 16-bit precision 4-input ADC by Jim Rowe
  12. Feature: Max’s Cool Beans by Max the Magnificent
  13. Review: Linshang LS172 Colorimeter by Allan Linton-Smith
  14. Back Issues
  15. Project: 2m VHF FM Test Signal Generator by Andrew Woodfield, ZL2PD
  16. Feature: Teach-In 2024 – Learn electronics with the ESP32 by Mike Tooley
  17. PartShop
  18. Market Centre
  19. Advertising Index
  20. Back Issues

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  • Raudive Voices Revisited (January 2023)
  • A thousand words (February 2023)
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  • Prophecy can be perplexing (May 2023)
  • Technology comes in different shapes and sizes (June 2023)
  • AI and robots – what could possibly go wrong? (July 2023)
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  • We both have truths, are mine the same as yours? (September 2023)
  • Holy Spheres, Batman! (October 2023)
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  • Good grief! (December 2023)
  • Cheeky chiplets (January 2024)
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  • The Wibbly-Wobbly World of Quantum (March 2024)
  • Techno Talk - Wait! What? Really? (April 2024)
  • Techno Talk - One step closer to a dystopian abyss? (May 2024)
  • Techno Talk - Program that! (June 2024)
  • Techno Talk (July 2024)
  • Techno Talk - That makes so much sense! (August 2024)
  • Techno Talk - I don’t want to be a Norbert... (September 2024)
  • Techno Talk - Sticking the landing (October 2024)
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Articles in this series:
  • Win a Microchip Explorer 8 Development Kit (April 2024)
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  • Net Work (July 2024)
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Articles in this series:
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  • STEWART OF READING (April 2024)
  • Circuit Surgery (May 2024)
  • Circuit Surgery (June 2024)
  • Circuit Surgery (July 2024)
  • Circuit Surgery (August 2024)
  • Circuit Surgery (September 2024)
  • Circuit Surgery (October 2024)
  • Circuit Surgery (November 2024)
  • Circuit Surgery (December 2024)
  • Circuit Surgery (January 2025)
  • Circuit Surgery (February 2025)
  • Circuit Surgery (March 2025)
  • Circuit Surgery (April 2025)
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  • Circuit Surgery (June 2025)
Articles in this series:
  • Audio Out (January 2024)
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Articles in this series:
  • Max’s Cool Beans (April 2024)
  • Max’s Cool Beans (May 2024)
  • Max’s Cool Beans (June 2024)
  • Max’s Cool Beans (July 2024)
  • Max’s Cool Beans (August 2024)
  • Max’s Cool Beans (September 2024)
  • Max’s Cool Beans (October 2024)
  • Max’s Cool Beans (November 2024)
  • Max’s Cool Beans (December 2024)
Articles in this series:
  • Teach-In 2024 (April 2024)
  • Teach-In 2024 (May 2024)
  • Teach-In 2024 – Learn electronics with the ESP32 (June 2024)
  • Teach-In 2024 – Learn electronics with the ESP32 (July 2024)
  • Teach-In 2024 – Learn electronics with the ESP32 (August 2024)
  • Teach-In 2024 – Learn electronics with the ESP32 (September 2024)
  • Teach-In 2024 – Learn electronics with the ESP32 (October 2024)
  • Teach-In 2024 – Learn electronics with the ESP32 (November 2024)
Circuit Circuit Surgery Surgery Regular Regularclinic clinicbybyIan IanBell Bell Topics in digital signal processing – digital-to-analog converter (DAC) outputs W e are looking at various topics related to digital signal processing (DSP). DSP covers a wide range of electronics applications where signals are manipulated, analysed, generated, stored or displayed as digital data, but originate from, and/or are output as, real-world signals for interaction with humans or other parts of the physical world. Fig.1 shows the key elements of a generic DSP system, with a signal path from an analog input via digital processing to an analog output. This does not necessarily represent every DSP system (nor are all the parts necessarily shown), but it serves are as reference for the various subsystems we will look at. Last month, we discussed the filtering requirements for antialiasing and reconstruction in a DSP system (these blocks are show in Fig.1). In previous discussions, we have looked at the input sampling process in some detail but have not considered the DAC output and reconstruction process in as much depth, so that will be our focus this month. Reconstruction filters As discussed last month, the spectrum of a sampled signal contains copies of the original signal (spectral images) centred on integer multiples of the sampling frequency (fs), as illustrated in Fig.2. If the bandwidth of the original signal (B) conforms to the Nyquist criteria, meaning that it is less than half the sample frequency, then the spectral images do not overlap and can, in theory at least, be removed by filtering to obtain the original signal. Analog In Antialiasing filter Sample and hold In Fig.2, the bandwidth the spectral image centred on fs extends down to fs – B, which is just higher than fs/2. Fig.2 also shows the response of an ideal ‘brick-wall’ reconstruction filter with a cutoff frequency of fs/2 that will remove the replica spectra centred on fs and higher frequencies. Of course, we cannot have an ideal filter in practice, but if the sampling frequency is above the Nyquist limit, there is some headroom to work with (as illustrated by the gap between +B and fs – B in Fig.2). However, this does not guarantee that the signal can be perfectly reconstructed with a filter that we could actually build. Ideally, the filter must completely remove the replica spectra, but the closer the sampling rate is to the Nyquist rate, the more demanding the filtering requirements become. Fig.3 shows a case where the filter passes the original signal fully but does not completely remove the first spectral image. If a lower cutoff frequency was used to remove more of the image, some of the original signal would be attenuated. In both cases, the signal is not perfectly reconstructed from the samples. There is a trade-off between the sampling rate and filter requirements. The higher the sampling rate is relative to the original signal bandwidth, the easier the filtering is by increasing the separation from the first spectral image (lower cost, simpler filters). However, higher performance is required from other parts of the system. xs(f) –fs–B –fs –fs+B –B –fs/2 Ideal reconstruction filter response +B fs–B fs/2 fs fs+B f Fig.2: A sampled signal spectrum with an ideal reconstruction filter response. xs(f) DAC output signal Real reconstruction filter response The discussion of the reconstruction process so far has assumed that Digital ADC the sampled waveform is a sequence of scaled impulses (idealised pulses that occur only at the sample time). However, the output from a DAC is not an ideal sampled waveform; it is a sampled-and-held signal, also called a zero-order hold. In the July 2024 issue, we discussed the sample-and-hold circuits that are commonly found at the inputs to analog­- to-digital converters (ADCs), as shown in Fig.1. These are required to capture the analog input signal and then hold a steady value while the ADC processes it. They typically use a capacitor with a voltage that follows the input until a switch isolates it, whereupon it retains the voltage it had across it at that instant. The DAC output has a similar waveform shape, but is produced by a different mechanism. The DAC will contain a digital register that holds the value to be delivered. The bits from this register will control electronic switches (transistors), or voltage inputs, to an analog circuit Digital processing Analog DAC Reconstruction filter Out –fs–B –fs –fs+B –B –fs/2 +B fs–B fs/2 fs fs+B f Fig.1: A generic digital signal processing (DSP) system structure. Fig.3: A sampled signal spectrum with a realistic reconstruction filter response. 22 Practical Electronics | October | 2024 The parameters vhigh and vlow set the maximum and minimum output voltages, and default to 10V. The logic signals default to a threshold of 0.5 (1 above, 0 below). The logic threshold can be changed by modifying the Ref parameter. The Rout parameter sets the output resistance and defaults to 1kΩ. This could cause problems with loading in some circuits if users are not aware of this. All the parameters are at their defaults for the circuit in Fig.4. DAC waveforms Fig.4: This LTspice schematic creates a sample pulse and sample-and-hold waveforms. that produces a voltage or current proportional to the binary value. There are various ways to do this, for example, a set of binary-weighted resistors or current sources, or ladders of resistors. When the register value is changed, the output will quickly step to the new value corresponding with the register contents. The output will be held constant between register changes, apart from the time it takes the circuit to react to register updates. It is useful to be able to create a sample-­and-hold waveform in LTspice, for example, to simulate the response of a reconstruction filter. In the July article, we simulated the sample-and-hold process using a couple of approaches. The first was a simple switch and capacitor following the basic structure of a sample-and-hold circuit, and the second used a model of a real ADC, simulating its sampling process. In the latter case, the output is an analog representation of the converted voltage, so it produces a sample-and-hold type analog waveform. page at ltwiki.org has information on this and other undocumented devices. The sample device has two modes of operation that depend on which control input is used (only one may be used at a time). The CLK input samples the input voltage and transfers it to the output when a positive edge (logic 0 to 1 change) occurs – this is used here. The S/H input provides track-and-hold functionality (like the capacitor-based circuit mentioned above). It operates in track mode at logic 1 and hold mode for logic 0. The sample device has some parameters that can be set by right clicking the schematic symbol and entering the text in the form parameter=value into the Value box (with parameter/value pairs separated by spaces). The circuit in Fig.4 creates a sample pulse train for a 1kHz sinewave sampled at 10kHz in a similar manner to previous examples. The sampling pulses also clock the sample-and-hold device, which creates a sampled-and-held version of the input waveform, as would be seen at the output of a DAC. The results are shown in Fig.5. The upper pane shows the original sinewave, while the second one below it is the sample pulse train and the third is the sample-and-hold (zero-order hold) waveform. The bottom pane shows the sample pulses and zero-order hold waveform together. The hold value changes to a value equal to each sample pulse amplitude, and remains at that level until the next sample point. We can use the circuit in Fig.4 to apply signals like a DAC output to a reconstruction filter to observe the performance of The sample device There is another option for a creating a sample-and-hold waveform in LTspice, which we will use here (see Fig.4). LTspice has a special function called “sample”, which is a behavioural sample-and-hold model found in the Special Functions folder of the component tool. This is an undocumented LTspice “A” type device (these have instance names starting with a letter A in the same way that, for example, resistor names all start with letter R). There is general information on these devices under “A. Special Functions” in the LTspice help, but the sample device is not included. However, some information is provided in an example schematic in the LTspice download, and the LTwiki Practical Electronics | October | 2024 Fig.5: These plots show the output of LTspice from the simulation shown in Fig.4. 23 Fig.6: An LTspice schematic of cascaded filters for reconstructing the DAC output. the filter. Fig.6 shows the filter we will use for this illustrating this. Again, we are using behavioural models from the special functions part of the library to create the filter quickly and easily. Of course, it can be replaced by any specific circuit design that might be of interest. Several of these behavioural filters are available; the one used here is 2ndOrdLowpass, which as the name suggests, is a second-order low-pass filter. The 2ndOrdLowpass device has three parameters that can be set by right clicking the symbol. These are the cutoff frequency (f0), the quality factor (Q), which sets the filter response type, and the gain (H). In this example, the cutoff frequency is 5kHz (half the sampling frequency), the Q factor is 0.707 for a Butterworthtype response, and the gain is 1. Three of these filters are used in series to create second-, fourth- and sixth­-order responses. Plots of the frequency responses from running an AC simulation on Fig.6 are shown in Fig.7. Reconstruction filter simulation Fig.8 shows the filters connected to the sample-and-hold output from Fig.4. The top pane shows the zero-order hold (DAC output) signal, while the lower pane shows the filter outputs with the same colours as Fig.7 (magenta for second order, yellow for fourth order and orange for sixth order). Given that the sampled signal was an ideal sinewave, the output of the reconstruction filter should also be a perfect sinewave. The second-order filter clearly fails to do this; the waveform is distinctly distorted. The fourth-order filter is much better, but these is still some distortion just about visible. The sixth-order filter output looks very good in this image. The three waveforms are offset in time due to the delays introduced by each filter stage. Fig.7: The filter responses from the circuit in Fig.6. Looking at the shape of sinewave does not provide much information about the quality of the signal unless it is quite heavily distorted. The spectrum of a signal, either from simulation or measurement using test equipment, provides a clearer picture of the signal quality and the nature of the any issues (eg, which unwanted frequencies are dominant). Fig.10 shows the spectra of the filter outputs from Fig.9. To obtain good results, the simulation time was extended, the minimum timestep reduced, and the SPICE directive (.option plotwinsize=0) was added to prevent compression of the waveform data (shown as comments in Fig.8). The spectra show the 1kHz wanted signal and the spectral images centred on one, two and three times the sample frequency. The 1kHz signal appears above and below the sample frequency multiples in the images, for example, at 9kHz and 11kHz for the first image centred on 10kHz. The three plots show the relative reduction amounts of the spectra images achieved by each filter. In this example, the signal frequency is moderately close to the Nyquist rate and the filter cutoff frequency is set to be at the Nyquist frequency. We see that a reasonably high-performance filter (sixth-order) may be needed. In practice, it depends on the desired level of accuracy of the output signal, and we Fig.9: The simulation results from Fig.8. Note the varying accuracy of the reconstructed sinewaves. Fig.8: This LTspice circuit illustrates the filtering of a zeroorder hold signal. 24 Practical Electronics | October | 2024 would have the option of using filter types with faster cutoffs than the Butterworth, that might be suitable at a lower order. As mentioned above, we can reduce the filtering requirements by using a higher sampling rate. This is illustrated in Fig.11, which uses the same simulation as Fig.8 but with the sampling rate increased to 50kHz – this is achieved by changing the Tperiod[s]: parameter of the V3 pulse source from 100µs to 20µs. We see that the second- and fourth-order filters produce good sinewave outputs with the higher sampling rate. This is the reason that most high-performance audio DACs these days are oversampling types, that operate at a multiple of the actual sampling rate to make the filter’s job much easier. But that is a topic for another column. DAC frequency response We have shown some simulations that illustrate the shape of the DAC output waveform and the effects of filter response and sampling rate on the reconstruction of a sinewave. This seems to indicate that if we have a sufficient sampling rate, a filter with a flat passband and a sufficiently sharp cutoff, we can more-or-less perfectly reconstruct the sampled signal, particularly if we can get close to the ideal case shown in Fig.2. However, this is the not whole story of using a DAC to reproduce a sampled waveform. A waveform’s spectrum depends on the shape of the waveform, but the shape of the idealised sample impulses and zero-order hold output from the DAC are not the same. This implies the DAC does not have a flat frequency response. It will modify the spectrum of the waveform away from that of the sampled data from the digital processing part of the system. Thus, the DAC can distort the waveform even in a system in which the samples are passed to an ideal DAC and brick-wall reconstruction filter. This effect is worse for lower sampling rates relative to the original signal, so increasing the sampling rate will mitigate the effects of the DAC’s frequency response. It also possible to compensate for the DAC’s response by suitable additional filtering. The sinc function The shape of a DAC’s frequency response relates to a mathematical function denoted sinc (pronounced in the same way as “sink”). The sinc notation is attributed to British mathematician Philip Woodward in 1952 (the function itself was used well before this). It is said to stand for “cardinal sine” (or Practical Electronics | October | 2024 Fig.10: Spectral plots of the output signals from the filters shown in Fig.8. Fig.11: The simulation results from Fig.8 with the sampling rate increased to 50kHz. sinus cardinalis in Latin), but that name was not used by Woodward and there is debate over the origin of the name – which might appeal to those who like exploring maths history and etymology (see https://pemag.au/link/ac00). The sinc function is defined as: sinc ( x )= sin ( x ) x ( πx )0/0, which When x is zero, wesinget sinc π ( x )= is mathematically problematic (due to πx the division by zero), so sinc(0) is defined to be 1. This is because sinc(x) tends towards 1 as x tends towards 0. This mathematical trick is called a removable singularity. ( x )variant is the sin A )= normalised sinc sinc( xfunction, which is dex fined as: sin ( πx ) sinc π ( x )= πx ...again with sincπ(0) defined to be 1. This function occurs frequently in DSP and telecommunications. It has the property that the points at which sincπ(x) is equal to zero occur at integer values of x and (for those who understand calculus), it has a value of 1 when integrated from minus to plus infinity (hence the term normalised). An obvious question is: why is a DAC’s frequency response a sinc function? As we have mentioned previously, the mathematical process of obtaining a spectrum from a waveform is called the Fourier transform. The answer, without going into too much detail, is that the Fourier transform of a rectangular function is a sinc function and the DAC output (zero-order hold) is effectively a set of rectangular pulses in the time domain, so the process 25 Simulation files Most months, LTSpice is used to support descriptions and analysis in Circuit Surgery. The examples and files are available for download from the PE website: https://bit.ly/pe-downloads Fig.12: An LTspice schematic for plotting the sinc() function. Fig.13: Sinc (green) and normalised sinc (red) plotted using the circuit shown in Fig.12. The values are numbers, not voltages. of outputting the samples with a DAC in the time domain translates to a sinc function in the frequency domain (the frequency response). As well as the frequency response of a DAC, the sinc function is important in the implementation of digital filters, so we will come across it again later in this series. Plotting the sinc function The shape of the sinc function can be observed by plotting it in LTspice. This is not really a normal use for LTspice, but it is straightforward using behavioural sources (see Fig.12) and may be useful if you do not have access to or xs(f) DAC frequency response (sinc) Fig.14: The DAC frequency response plotted by LTspice. The values are numbers, not voltages; the X-axis is ƒ/ƒs. familiarity with other tools. The plots are achieved by using a voltage source, V1, to produce a signal x (for the x-axis) controlled by a DC sweep analysis, which steps the value of x over the desired range (-20 to 20 in this case). The behavioural sources calculate the value of the sinc function at each point in the DC sweep. The expression used in the behavioural sources for the sinc and normalised sinc function respectively are: The results are shown in Fig.13 – these are just numerical values, although LTspice plots them as voltages. The actual DAC frequency response is obtained using x = f/f s­ in the normalised sinc function and taking the absolute value (ignoring the sign). f is the frequency in the DAC output signal spectrum and fs­is the sample frequency. This is plotted in Fig.14 using the circuit in Fig.12 modified with the following expression in the B1 behavioural source: V=sin(V(x))/V(x) V=sin(pi*V(x))/(pi*V(x)) V=abs(sin(pi*V(x))/(pi*V(x))) Original sampled signal spectrum 0 DAC response gain (linear) 1.0 0.8 0.6 0.4 0.2 0.0 f fs/2 fs 2fs Nyquist Fig.15: The DAC frequency response (sinc function) with a generic sampled signal spectrum, using a linear scale for the DAC response. DAC frequency xs(f) response (sinc) 0 fs/2 Nyquist DAC response gain (dB) Original sampled signal spectrum fs 2fs f 0 –10 –20 –30 –40 –50 –60 Fig.16: The same plot as Fig.15 but with a logarithmic scale for the DAC response. 26 The x axis represents f/fs­and we see that the value is zero at integer multiples of the sample frequency (f/fs­= 1, 2, 3 etc). Fig.15 shows the DAC frequency response superimposed on the generic sampled signal spectrum used in Figs.2 & 3. Only the positive part is shown to save space. The plot shows how the DAC response aligns with the signal spectrum. Remember that we only want the part of the spectrum up to the Nyquist frequency (fs­/2); the rest should be removed by the reconstruction filter. Over the wanted range, we see that the effect of the DAC’s frequency response is to attenuate the higher signal frequencies. Fig.15 plots the DAC response on a linear scale; it is taken directly from the relevant part of Fig.14, scaled appropriately. Fig.16 shows the DAC response plotted on a decibel (dB) scale. The DAC response goes to zero at fs­and 2fs­, which is minus infinity on the dB scale and beyond the axis range of −60dB, hence the gaps. We will continue to look at DACs and their output signals next month. PE Practical Electronics | October | 2024