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By Andrew Levido Precision Electronics Part 6: Digital-to-Analog Conversion The first five parts of this series have concentrated on sources of error & imprecision in analog circuitry, such as gain errors, offset voltages, bias currents & noise. These days, most analog circuitry eventually interfaces with the digital realm, such as with a microcontroller, so we also need to understand the precision approach to ADCs & DACs. I n this series so far, we have covered precision electronics from a purely analog perspective. We designed a simple multi-range current-sensing circuit that could be used in a bench-top power supply. It had an analog precision of around ±0.06% at 25°C after trimming out fixed errors. The idea was that the analog measurement voltage would be digitised via an analog-to-digital converter (ADC), with the trimming and calibration carried out digitally. We will therefore ultimately need to design an ADC subsystem that will have similar or better performance to the analog circuitry we have already developed. However, the topic of interfacing digital and analog electronics is a big one and quite complex. So I am going to cover it over two articles, starting here with some general principles and then taking a look a digital-to-analog converters (DACs) with a real-world example, before moving on to ADCs next month. We will also need to take a look at voltage references in a later article, since any discussion of ADCs/DACs would be otherwise incomplete. Quantisation errors A digital system like a microcontroller has to represent an analog quantity using a binary-coded number. This can be a simple unsigned integer (zero or a positive whole number) if we are representing a quantity that is always positive, or an offset binary or signed (two’s complement) integer if the quantity can be both positive and negative. Table 1 shows how typical ADCs and DACs represent such quantities, using 8-bit numbers as an example. Notice that the resolution of the two’s-complement and offset integers are lower because the input span is twice the full scale value. It might seem obvious, but you need to take this into account when choosing a converter. It’s all too easy to fall into the trap of thinking about Fig.1: the relationship between analog input or output and digital code for an ideal 3-bit converter. (b) is more representative of real-life devices where the quantisation error is usually ±½LSB. (a) 64 Silicon Chip (b) Australia's electronics magazine full-scale instead of span in these circumstances. In an ideal converter, the relationship between the analog input or output and the digital code will be as shown in Fig.1. The horizontal axis is the digital code (in this case, three bits for simplicity), while the vertical scale is the analog value as a fraction of full scale. The green line represents an ideal transfer function, but since the digital codes are discrete, there must be transition points, shown by the black dots. Taking the chart on the left as an example, for an ADC, the code would be zero for an input of zero volts and it would remain so for input voltages up to ⅛ of full scale, at which point there will be a transition to the 001 code. For a DAC, the output voltage will be somewhere below ⅛ of full scale if the code is 000. It’s obvious that there is a degree of error inherent in any such converter, since the transition points The vertical axes in Figs.2a-2d are the analog voltages. (a) siliconchip.com.au Table 1 – ADC and DAC numerial coding schemes Voltage Unsigned Integer Two's Complement Offset Binary +Full Scale 11111111 01111111 11111111 +Full Scale − 1 ... 11111110 ... 01111110 ... 11111110 ... +1 00000001 00000001 10000001 0 00000000 00000000 10000000 −1 ... – ... 11111111 ... 01111111 ... −Full Scale + 1 – 10000001 00000001 −Full Scale – 10000000 00000000 are separated by one least significant bit (LSB) of the input code. This is called quantisation error and is an inescapable consequence of the discrete nature of digital systems. In this example, the quantisation error at any point on the transfer function will be somewhere between zero and one LSB. The chart on the right side of Fig.1 is a more realistic example of how a converter is configured; the ideal transfer function is the same, but the transitions are shifted ½ of one LSB so that they occur between the nominal analog values. In this case, the quantisation error is the same magnitude, but is ±½ LSB either side of the nominal value. Quantisation error can add noise to an AC signal. If we were to apply a linear ramp signal to an ADC, or try to generate a linear ramp with a DAC, the error would look like that shown at the bottom of Fig.1b. The quantisation error would appear as a sawtooth wave with an amplitude of ±½LSB. We can calculate the signal-to-noise ratio (SNR) of a digitised sawtooth or triangular waveform. If we have a converter with n bits, the maximum amplitude of an AC waveform can be ½ × 2n LSB. The noise amplitude is ½LSB, so the SNR is 20log10(2n) or approximately 6.02n decibels. But this only applies to sawtooth and triangle waveforms where the signal has a uniform error distribution. For sinewaves, we have to use the approximation SNR = 1.76 + 6.02n decibels to allow for the uneven error distribution. For an 8-bit converter, the SNR due only to quantising will be around 50dB, and for a 12-bit converter, it will be 74dB. This is pretty significant; hence, high-fidelity audio ADCs and DACs use many bits and careful filtering to maximise the SNR. Quantisation error is therefore defined by the resolution of the converter. You obviously need to select a converter with sufficient bits to give you the resolution that your application requires. Typically, you need even more bits to account for some of the other errors that can occur. Further ADC & DAC errors You will see ADC and DAC errors expressed in a range of terms, so it can be a bit confusing at first. We have already seen quantisation error expressed in least significant bits (LSB), but you will also see errors expressed as relative errors (percentages or parts per million) and in absolute terms like millivolts. You can convert LSB to a percentage error by dividing it by 2n (where n is the number of bits, ie, the resolution) and applying the appropriate scaling. For example, the ½LSB quantisation error on an 8-bit converter will be about 0.2% (100% × ½ ÷ 28), while on a 12-bit converter, it would be 122ppm (106 × ½ ÷ 212). We have seen in past instalments that it can be useful to have errors in both absolute and relative terms, depending on whether we are adding or multiplying uncertain quantities. Fig.2 shows the four most common types of error that are relevant for ADCs and DACs. Offset error (Fig.2a) is a fixed shift in transition points away from their ideal locations. If measured in LSB, it is defined by the difference between the value of the first code transition and its ideal value. It is most often specified as an absolute voltage, just like an op amp’s offset voltage. As you might expect, there can also be a gain error (Fig.2b) if the slope of the transfer function deviates from the ideal. In LSB, it is defined by the Fig.2: ADCs and DACs have four main types of error shown in these graphs: offset error, gain error, integral nonlinearity (INL) and differential nonlinearity (DNL). If the DNL exceeds ±1LSB, the converter can exhibit non-monotonicity, as shown in (d). (b) siliconchip.com.au (c) Australia's electronics magazine (d) April 2025  65 difference between the last code transition point and its ideal counterpart, but it is more often specified as a relative error. There is also the possibility that the transfer function will deviate from the ideal by not being completely linear (Fig.2c). There are two common measures of linearity error: differential nonlinearity (DNL) and integral nonlinearity (INL). INL is the maximum deviation of the transfer function from the ideal over the whole conversion range, while DNL is the maximum difference between the width of a code and its ideal width (1 LSB). A DNL of more than ±1LSB implies a loss of monotonicity, as shown in Fig.2d. A monotonic curve is one that always increases (or decreases). Fig.3: a resistor string DAC has 2n matched resistors forming a voltage divider. Analog switches select one ‘tap’ off this divider for each input code. A 16bit DAC of this type will have 65,536 matched resistor and a similar number of analog switches! Fig.4: an R-2R DAC uses just 2n matched resistors and switches to achieve 2n output voltage steps. This architecture is also useful for lowresolution ‘roll-your-own’ DACs using microcontroller GPIOs in the place of the analog switches. 66 Silicon Chip The INL is the specification to care about if you are looking for the best overall accuracy – for example, to generate or measure a voltage with minimal error. However, if you are using the DAC or ADC in a control loop, you may want to focus on DNL. The control loop’s servo action will look after the INL if it is relatively ‘smooth’, but ‘patches’ of inconsistent gain (or worse, non-monotonicity) can cause control glitches like dead spots or even points of instability. Total unadjusted error The ‘total unadjusted error’ (TUE) is a figure that describes the total maximum error for a converter. This is very handy for calculating the error budget. Sometimes manufacturers specify the TUE in the data sheet – either in LSB or as a relative error – but you can calculate it yourself if necessary. To do so, you convert the offset, gain and INL errors to the same format, and add them using the root-sumof-squares method (since the error sources are uncorrelated). We will do this for our DAC example later in this article. Resistor string DACs Enough theory – let’s take a look at a few practical DACs. One common (and fairly obvious) way to construct a DAC is with a resistor string, as shown in Fig.3. A string of 2n equal-value resistors are used together with a set of binary-weighted analog switches to switch one ‘tap’ of the string to a buffer and out to an external pin. The output voltage is Vref(N ÷ 2n), where n is the DAC resolution in bits and N is the input code, which ranges from zero to 2n – 1. This type of DAC is guaranteed monotonic by design, and can have quite good linearity since it is possible to match on-chip resistors well. They can also have good temperature stability for the same reason. It is possible to get DACs with up to 16 bits of resolution that use this architecture. The AD5689 we will use in our test circuit is a good example. This means the chip contains a string of 65,536 matched resistors and a similar number of double-throw analog switches, or equivalent, for each channel. Amazing! R-2R ladder DACs The R-2R ladder is a variant on the Australia's electronics magazine resistor string DAC that uses a lot fewer resistors. Instead of requiring 2n resistors, we can get away with just 2n, using the circuit shown in Fig.4. Only one double-throw analog switch is required for each bit. The simplified circuit means you can get R-2R DACs with up to 20 bits or more of resolution. They also can have quite good linearity and temperature coefficients. The output voltage is Vref(N ÷ 2n), just like the resistor string DAC. Another useful property of the R-2R ladder DAC is that you can easily improvise one with an op amp, a handful of resistors and a few digital outputs. The analog switches in Fig.4 effectively switch between Vref and 0V, so they could be replaced with totem-pole digital outputs (say, microcontroller GPIOs), creating a basic 3-bit DAC. The performance will be average, since the reference voltage will be the digital supply voltage and you will probably use 1% resistors, but if you only need a few levels, this can be a handy technique to create a ‘free’ DAC. Current output & multiplying DACs A variation of the R-2R ladder DAC that provides an output current rather than a voltage allows us to build ‘multiplying DACs’. Strictly speaking, all DACs effectively multiply the reference voltage by the digital code, but many have internal references or external ones that only accept voltages of one polarity. A multiplying DAC can operate in two or four quadrants, as shown in Fig.5. In both cases, the DACs, shown inside the dashed box, are identical. Since the Iout pin is sitting at 0V courtesy of op amp IC1, the current coming out of the pin is N ÷ 2n × Vin ÷ R. You can see from the circuit that this equation will hold even if Vin is negative (in which case, the current will flow into the pin). This current is converted to a voltage by IC1, which is configured as an inverting amplifier. The output voltage of the two-quadrant multiplying DAC will be -N ÷ 2n × Vin, where Vin can be positive or negative. You will notice that the feedback resistor is provided within the DAC IC and is matched to the resistors in the siliconchip.com.au Fig.5: multiplying DACs use a current source architecture to achieve twoquadrant or four-quadrant operation. In both circuits, the reference can be of either polarity or an AC voltage. R-2R ladder. This is important because the semiconductor manufacturing process can produce on-chip resistors that are very well matched in value or ratio, but their absolute value is more difficult to control. Using an external resistor would almost certainly introduce large gain errors and poor temperature stability. Fig.5 also shows a four-quadrant version of the same circuit, which is identical in operation to the two-quadrant one but has an added (inverting) summing amplifier stage (IC2) that scales up the DAC output and offsets it by Vin. If we consider the code to be a signed value using the offset binary representation, we can effectively multiply a bipolar input voltage by a positive or negative integer. Multiplying DACs can be very useful in signal processing, for example, as a very fine-grained programmable gain stage. They are also useful in making precise ratiometric measurements. For example, if you excite some sensor (such as strain gauge) using a voltage produced by a multiplying DAC and digitise the resulting signal with an ADC that uses the same voltage reference, any error or drift in the reference is cancelled. The resulting readings are the true ratio of input to siliconchip.com.au output independent of the excitation voltage. Delta-sigma DACs Another class of DACs worth mentioning are the delta-sigma converters that you frequently encounter in audio applications. Delta-sigma DACs typically have very high resolution (20+ bits) to minimise quantisation noise and have spectacular linearity to ensure low harmonic distortion. We don’t normally use delta-sigma DACs in precision applications because their DC performance is generally not great, probably because this does not matter in audio applications. Oddly, there are plenty of very high-precision delta-sigma ADCs that work very well at DC, as we shall see next time. Pulse-width modulation We should not neglect pulse-width modulation (PWM) as a potential type of DAC, especially in microcontroller circuits where dedicated PWM peripherals are commonplace. Fig.6 shows the simplest possible configuration with a PWM output and an RC low-pass filter. The time constant of the low-pass filter has to be much longer than the PWM period (Tpwm) to produce an average of the PWM waveform Australia's electronics magazine Fig.6: a PWM DAC can be as simple as a microcontroller’s PWM output and an RC filter. The lower circuit uses a complimentary PWM signal to improve ripple and settling time eightfold. proportional to its duty cycle. A longer time constant with respect to Tpwm means better averaging and a lower output ripple. The worst-case ripple occurs at 50% duty cycle and is given by Vripple = Vfs(Tpwm ÷ 4RC). The downside of having a long time constant (and lower ripple) is a slow response of the output voltage to changes in the PWM duty cycle. Stephen Woodward published a really neat technique to address this problem in an EDN article published in 2017. Woodward showed that the time for the output voltage to settle to within the ripple voltage for a given change in duty cycle is Tsettle = RC × loge(Vfs ÷ Vripple). If we wanted to make a PWM DAC equivalent to a conventional DAC with 8-bit resolution, we would require that the peak-to-peak ripple be 1LSB (or 1/256 of the full-scale voltage), corresponding to the quantising noise. The first equation above tells us this requires an RC time constant 64 times the PWM period. The settling time (from the second equation) will therefore be 355 × Tpwm. Depending on what you are doing, that could be a long time! For 10kHz PWM, this is a settling time of 35ms. If you wanted a 10-bit resolution, the settling time would be even worse at 177ms. April 2025  67 Woodward’s ingenious solution is shown at the bottom of Fig.6. Here, an inverted version of the PWM signal is injected into the output via a series RC network to cancel the ripple. I have shown this coming from a complimentary PWM output on the microcontroller, but a logic gate inverter would work equally well. If the new resistor and capacitor are the same value as the original ones, the ripple equation becomes Vripple = ½Vfs × (Tpwm ÷ 4RC)2 and the settling time becomes Tsettle = ½Tpwm × √(Vfs ÷ Vripple) × loge(Vfs ÷ Vripple). Using the 8-bit example above, the RC time constant required to achieve the ripple target reduces from 64 to just four PWM periods, and the settling time reduces from 355Tpwm to 44Tpwm (or 4.4ms at 10kHz). This is an eightfold improvement in settling time! In the 10-bit case, the settling time reduces to 11ms from 177ms for the original circuit. It turns out you don’t even need precision components to achieve these improvements. It is sufficient to use 1% tolerance resistors and 10% tolerance capacitors. This is a circuit well worth knowing. Other DAC types If we agree that a duty-cycle-to-­ analog converter like the PWM example above is a form of DAC, we should also consider a frequency-to-voltage converter to be one too. Fig.7 shows a typical example using an LM331 IC. This circuit works as follows. A square wave of frequency Fin is differentiated by the RC network connected to pin 6, creating negative-­ going spikes on each falling edge. When these fall below the threshold set by the resistor divider connected to pin 7, the upper comparator sets the RS flip-flop. When the flip-flop is set, the discharge transistor on pin 5 is switched off, and capacitor Ct begins to charge via Rt. When this voltage reaches 2/3Vcc, the lower comparator resets the flip-flop, discharging Ct. This means the flip-flop is set for a fixed duration each time a falling edge on the input occurs. The analog switch connected to the flip-flop’s output directs a fixed current out of pin 1 during this period. The current is converted to a voltage by Rl and averaged by the RlCl lowpass filter. Fig.7: a frequency-to-voltage converter is also a useful type of DAC. This circuit shows how an LM331 can be used to create a simple but quite respectable DAC. 68 Silicon Chip Australia's electronics magazine The level of this current is precisely controlled by the circuit connected to pin 2. An on-board bandgap reference and op amp ensure a precise 1.9V is always present on pin 2, meaning a current of 1.9V ÷ Rs flows out of this pin and therefore out of the current mirror to the analog switch. A practical example Fig.8 shows an extract of a circuit I designed some time ago for a precision instrument. This part of the circuit includes a voltage reference, a two-channel DAC and a couple of op amps. The output is intended to be a ±2.0V precision voltage programmable by the microcontroller. I will step through the operation and error analysis for this circuit, so it will be helpful to follow both the schematic and the error budget (Table 2). The operating temperature range for this device is 15-35°C, reflecting its intended use in a laboratory setting. The MAX6225 provides a very stable, very accurate 2.5V reference (±200ppm initial accuracy, ±2ppm/°C). An inverted copy of the reference is provided by the inverting amplifier (IC1), an LTC2057 zero-drift op amp. The inverting op amp uses relatively high value resistors (10kW) to minimise the load on the precision reference. These resistors are high-precision (0.01%) types with very low thermal drift (±5ppm/°C), since we don’t want to compromise the performance of an expensive reference. The LTC2057 has very low input offset voltage (±4µV) and even lower offset drift (±15nV/°C), as we would expect from a “zero drift” op amp. Because we have used relatively high value resistors, I have included the op amp’s input offset current error in the table on line 3. You can see from line 4 of the table that the total error at the input of the reference inverter is dominated by the reference error and is 0.02%. You can see why I selected 0.01% resistors for this circuit – to keep the gain error down to a similar order of magnitude as the reference error. This leads to a total error for the negative reference of 0.047% over the temperature range, compared to a total error of 0.022% for the positive reference. I was not 100% happy with the negative reference error, but figured that as I was only making a handful of these siliconchip.com.au Fig.8: this is an excerpt from a circuit which uses a voltage reference, a DAC and a couple of op amps to create a programmable ±2V with a resolution of less than 200µV. The untrimmed error is better than ±0.03%. devices, my results would likely be much better. The odds of two identical resistors being at the opposite extremes of tolerance are low enough that if I did find an outlier, I could manually select resistors to fix it. The measured results show both references to be within 0.01% of each other on the prototype. The positive 2.5V reference is applied to the DAC. I used a very nice dual-channel, 16-bit resistor-string DAC. It can be configured for a gain of one or two. I used a gain of two to make the subsequent circuit design simpler. This means the full-scale output is 5.0V. In this configuration, the DAC has an offset error of ±1.5mV, a gain error of 0.1% and an INL of ±1LSB. Thanks to the manufacturer for specifying the three key figures in three different ways! That said, this is pretty good performance for a DAC, especially the INL. I converted all these figures to relative errors in the table and added them using the root-sum-of-squares method to arrive at a TUE of 0.104%, dominated by the gain error. The data sheet actually provides a TUE figure of 0.1%, so I did this exercise to just demonstrate how TUE is calculated. It is nice when theory and reality agree! Table 2: positive/negative voltage references, DAC & offset amp errors Error Since the voltage at the output of the DAC is the reference multiplied through the DAC coefficient, the total error is calculated as the sum of relative errors on line 12. We get a total error here of 0.127% over the full temperature range (0.124% + 0.003%), dominated by the DAC gain error of 0.1%. I’m not usually a proponent of ‘typical’ specifications, but if our DAC was within the typical range, the total error would be closer to 0.05%. Finally, the 0-5V DAC output is summed with the negative reference (and inverted) by IC2. This produces an output voltage that ranges from +2.5V when the DAC code is zero At Nominal 25°C Additional error over 15-35°C (Nominal ±10°C) Nominal Value Abs. Error Rel. Error Abs. Error Rel. Error 1 MAX6225ACASA+ (±200ppm, ±2ppm/˚C) 2.5V 500μV 0.02% 0.002% 2 Op Amp: LTC2057 (Vos ±4µV, 15nV/˚C) 0V 4μV 100nV 3 Op Amp Ios × 10kW || 10kW: LM7301 (Ios ±400pA, ±1pA/˚C) 0V 2μV 50nV 4 Voltage at Op Amp Input (Line 1 + Line 2 + Line 3) 2.5V 506μV 5 Op Amp Gain: R/R Stackpole RNCF0603TKY10K00 (0.01%, 5ppm/˚C) 1 6 +Vref error (Line 1) 2.5V 500μV 0.02% 50μV 0.002% 7 −Vref error (Line 4 × Line 5) 8 DAC Offset error: AD5689 (±1.5mV, ±1µV/˚C) -2.5V 1mV 0.04% 175.2μV 0.007% 5V 1.5mV 0.03% 10μV 0.000% 0.02% 50μV 50.2μV 0.02% 0.002% 0.005% 9 DAC Gain error: AD5689 (0.1%, ±1ppm/˚C) 2 0.1% 0.001% 10 DAC Linearity: AD5689 (INL ±1LSB, DNL ±1LSB) 0 0.002% 0.000% 11 DAC total unadjusted error (root sum of squares Lines 8-10) 5V 5.2mV 0.104% 51μV 0.001% 12 DAC total error (Line 6 × Line 11) 5V 6.2mV 0.124% 620μV 0.003% 13 Op Amp: LTC2057 (Vos ±4µv, 15nV/˚C) 0V 4μV 150nV 14 Op Amp Ios × 1kW || 1kW || 1kW: LM7301 (Ios ±400pA, ±1pA/˚C) 0V 133.2nV 3.3nV 15 Op Amp Gain: R/R Stackpole ACASA1002U1002P1AT (0.05%, 5ppm/˚C) 1 0.05% 0.005% 16 Voltage at Op Amp Input (Line 7 + Line 12 + Line 13 + Line 14) 2.5V 7.2mV 0.29% 250.6μV 0.01% 17 Voltage at Op Amp Output (Line 15 × Line 16) 2.5V 8.5mV 0.34% 375.6μV 0.015% Silicon Chip kcaBBack Issues $10.00 + post $11.50 + post $12.50 + post $13.00 + post January 1997 to October 2021 November 2021 to September 2023 October 2023 to September 2024 October 2024 onwards All back issues after February 2015 are in stock, while most from January 1997 to December 2014 are available. For a full list of all available issues, visit: siliconchip.com.au/ Shop/2 PDF versions are available for all issues at siliconchip.com.au/Shop/12 (0x0000), to almost -2.5V when the DAC code is full scale (0xFFFF). The error budget for this circuit is similar to the previous examples. This time, I used low-cost resistor arrays with ±0.05% tolerances on the matching. If I had used individual 0.01% resistors for this, there would be a 0.03% error due to there being three resistors involved. The improvement of 0.02% does not justify the extra cost given the other sources of error in the circuit. There are a couple of things worth noting before we discuss the results this circuit produced. First, you will see that I am only using a range of ±2V, not the full ±2.5V the circuit is capable of. This is because near zero and full scale, the DAC output is prone to errors, since these are right at its power supply rails. We already know that no output can truly swing all the way to the rails. Avoiding the ends of the span costs us some precision, since the whole range of codes is not used. In this case, the valid codes are 6553 to 58,981 for a 4V span, giving us a resolution of about 191µV, which is plenty for my application. You should always avoid the extremes of DAC & ADC ranges in precision applications. You can go much closer than I have here, but there will probably be errors right at the edges. I have also taken a lot of care with the power supplies. It is not worth spending good money on precision components and skimping on the power supply. The digital and analog supplies come from separate linear regulators. I included a ferrite bead on the analog supply to the DAC, more to protect the rest of the circuit from glitches caused by the DAC switching than vice versa. Results I first measured the positive and negative references and found they were +2.50015V and -2.49989V, both well under 0.01% away from the nominal value and within 0.01% of each other. I measured the output voltages at code intervals of 400 hexadecimal (1024 decimal) over the full range. With a code of zero, I measured +2.49930V (0.028% error). At 0x8000, I measured 481µV (0.019% error), while at full scale (0xFFFF), I measured -2.45720 (-1.7% error). As mentioned above, we expect the extremes to be poor. If we look at the range of interest, the error is never worse than +0.024%; in fact, it is also never less than +0.018%, suggesting we have an offset error, albeit a small one. Sure enough, the absolute error ranges from 460µV to 610µV and averages 550µV. Can we trim this error somehow? My circuit also includes an ADC, and switching that allows me to measure the voltage we are concerned with. If we were to measure the voltage with the code 0x8000 (corresponding with 0V out), we would be able to measure the 481µV offset and correct for it in software. We could similarly measure the voltage at either end of the span (±2V nominal) and correct for that. This is easier said than done, and we will look into it in more detail in a later article. I also performed a full noise analysis of this circuit, which I have included in Table 3. I won’t go into the gory details since I used the same techniques I described in the last article. Overall, the RMS noise voltage should be around 1.4µV over a 10Hz bandwidth. That does not include quantisation noise, since this is a DC application. The biggest contributor is the DAC noise, with the reference coming in next. Given the 191µV resolution of the DAC, this level of noise is not going to impact the precision of our circuit. In summary, we can almost certainly get to an overall precision close to that of the reference at 0.02%, and it is pretty hard to do any better than SC that! Table 3 – noise analysis with 10Hz nominal bandwidth Noise Source Notes Noise Voltage (RMS) 1 Positive reference noise MAX6225 (15nV/√Hz, fc100Hz) fb straddles fc so use f = fb + fcloge(10) = 240Hz 232.4nV 2 Ref inverter amp voltage noise: LTC2057 (11nV/√Hz) Data shows noise flat from 0.1Hz to 10Hz 34.8nV 3 Ref inverter amp voltage noise: LTC2057 (170fA/√Hz) 10kW || 10kW resistors in inverting input 2.68nV 4 Ref inverter 10kW input resistor & feedback resistor √4kTRfb 40.7nV 5 Negative reference noise Line 1 + Noise Gain (2) × Line 2 # 237.5nV 6 DAC noise AD5689 (300nV/√Hz) Use fb = 10Hz 948.7nV 7 DAC output noise Line 6 + Line 1 1.2µV 8 Summing amp voltage noise: LTC2057 (11nV/√Hz) Data shows noise flat from 0.1Hz to 10Hz 34.8nV 9 Summing amp voltage noise: LTC2057 (170fA/√Hz) 10kW || 10kW || 10kW resistors in inverting input 1.79nV 10 10kW input resistors & feedback resistor √4kTRfb 40.7nV 11 Scaled output noise Line 7 + Line 5 # 1.4µV # other errors are at least an order of magnitude smaller, so they can be ignored 70 Silicon Chip Australia's electronics magazine siliconchip.com.au