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Circuit Surgery Regular clinic by Ian Bell Differential amplifiers R ecently, on EEWeb’s forum, comprises a differential amplifier formed by Q1 and Q2, biased by the current source formed by Q6 and Q7, and connected to an active load formed by Q3 and Q4. Q6 and Q7 form a current mirror, with Q6 providing the reference for Q7 to deliver the bias current to the differential amplifier. The second stage is a common-emitter amplifier using Q5, for which Q8 is an active load. Q8 is a current source to provide bias and act as a high resistance load; like Q7 its reference is provided by Q6. We discussed the common-emitter amplifier with active loads in a recent Circuit Surgery article (PE, December 2019) so we will focus on the differential amplifier in this article. Robinson-Constantin Chera posted a question asking about simulating an amplifier circuit, writing: ‘I need to implement the following circuit [Fig.1] in LTspice but I don’t know what VCM, Vg, VCC and C infinite are... Can you help me with the symbols for it?’ This is a basic operational amplifier (op amp) type circuit; or more specifically, the initial gain stages of an op amp without the power-amplifying output stage. The circuit is typical of those designed for implementation as integrated circuits (ICs), where transistors are used wherever possible and resistors are kept to a minimum. The amplifier only uses one resistor (R2) the other resistor in the schematic (R1) is a load and the capacitor (C ∞) is also part of the load. Circuits like this can look like an impossible mass of transistors if you are not familiar with the various building blocks which are used – so Fig.2 highlights the various sections. The following outlines the circuit’s structure (also refer to Fig.2) – if the terminology here is not all familiar, don’t worry because we will explain its operation in more detail later. The amplifier has two stages. The first stage Spicing up the circuit Robinson-Constantin posted a couple of LTspice schematics on the forum and received feedback. We will not look at those specifically, but will discuss some general issues about setting up this (and similar circuits) for simulation. The schematic in Fig.1 is a typical ‘textbook’ circuit (we will refer to it as such, although of course the source may be a web page). The aim of such circuits is often to explain operating principles, and some things may be left out to simplify the explanation or focus on a particular aspect, which may lead to problems with simulation. Textbook circuits may be idealised to facilitate a discussion of key points without getting bogged down in complexities. SPICE can simulate highly idealised circuits, but the assumptions may not match reality, particularly with active devices such as transistors, which again, may cause problems. This will be more likely if ‘real’ transistors are used in the simulations (models of actual devices), as Robinson-Constantin did. Default models match NPN and PNP transistor characteristics, which is unlikely with real device models – the circuit may ‘unbalance’ and fail – typically one or more transistors may get stuck in saturation. Similar issues were discussed in the December 2019 article on active loads. Even the default transistor models may not give the desired results without some tweaking to match what is implied by any assumptions. Before worrying about these things, you need to set up the schematic – copying the basic schematic from the textbook is probably straightforward, but you may need to add components Active load f or dif f erential amplif ier Common-emitter amplif ier V CC V CC Q 3 Q 3 Q 4 Q 1 Q 2 V CM Q 5 v i1 C v g Q 6 R2 Q 5 R2 Q 8 Q 1 Q 2 v i2 Dif f erential amplif ier V CM Q 7 Q 4 R1 V O Q 7 Q 6 V O Q 8 Current sources f or b ias Q 3 also active load f or Q 5 Fig.1. Robinson-Constantin Chera’s amplifier circuit. Practical Electronics | September | 2020 Fig.2. The circuit in Fig.1 with the various building blocks identified. 43 to account for the input signals, power supplies and loads. Robinson-Constantin asks about VCM, Vg and VCC – these are the inputs signal (VCM, vg) and supply (VCC). The value of VCC was not specified in the original post, but later 10V was used. It is often a good idea to simulate circuits with a load, even if the value is idealised (eg, to a very large value) while the basic operation is confirmed. Changing the load’s value will provide insight to the circuit’s performance. In Fig.1, R1 is the load and C∞ is a coupling capacitor which is chosen to have a much lower impedance than R1 at the frequencies of interest. If this condition is met then the specific value is generally not very important in a simulation. In textbooks, supplies are often just labelled (eg, V CC in Fig.1), but for a simulation you will need to put voltage sources on the schematic to account for each power supply – in this case there is only one, but split supplies are common, and some circuits have multiple supply voltages. Differential signals The circuit in Fig.1 is a differential amplifier, so it has two inputs and we can use two voltage sources in the simulation to set up the input signal. Differential signals are carried on two wires, so the signal of interest – the signal we want to amplify – is the voltage between the two wires. For example, this could be 1mV, but the individual voltages could be −0.5mV and +0.5mV or 1.9995V and 2.0005V, or an infinite number of other possibilities. The voltage difference does not completely describe the situation, we also need to specify the average value of the two voltages, called the common-mode voltage, which is 0V and 2V respectively in the two examples. In Fig.1 the common-mode voltage is applied to the two inputs with two equal VCM DC voltage sources. Having established the common-mode voltage, the wanted signal – the difference – can be applied using a signal voltage source on one of the inputs. Exactly the same setup can be used in the simulation, but actually only one SPICE voltage source needs to be use per input because one can be set to be DC at VCM and the other to be a sinewave source of amplitude vg with a DC offset of VCM. Alternatively, we can use two DC-plus-sine sources with 180°-out-of-phase sinewaves of the same frequency and half the amplitude of the desired differential input signal. Differential-input circuits such as op amps can only operate over a limited range of common-mode voltages, and the circuit in Fig.1 is no exception. We must use a suitable value and 0V might seem like a simple option, but 44 it will not work for Fig.1. Unlike many basic op amp examples, which use a split positive and negative supply with 0V in the middle, the circuit in Fig.1 operates on a single supply, so VCM = 0V would switch off the transistors in the amplifier – it would not work. We need VCM to be about half the supply voltage for optimal operation. Similarly, we need to set a suitable value for vg, which we will discuss later. Current sources As indicated above, in ICs, circuits based on transistors are typically more economical and provide better performance than using resistors. Basic transistor amplifiers use resistors (for example, a potential divider connected to the base) to set the operating point – the current flowing in the transistor with no signal present. Instead of using resistors, the operating point can be set by using a circuit which sets up a constant current, equal to the operating point current, into the transistor. During operation the transistor’s total current will vary around this point as the signal changes, just as it does with resistorbased biasing. The circuit in Fig.1 uses a basic current source – a two-transistor current mirror, as shown in Fig.3, where the transistors have been labelled to match their role in Fig.1. The base-emitter voltages (V BE) of the two transistors are exactly equal because they are connected directly together, so if the transistors are identical, and have the same environmental conditions (in particularly their temperatures are equal), then the currents in both devices, which are controlled by VBE, must be equal. It follows that two currents IIn and Icopy in Fig.3 are almost equal. They are not exactly equal because some of I In is diverted to provide the base currents, but this is typically a very small proportion (typically 1/50 to /100 or less), so values are very close. If we apply a current (IIn) to Q1 we get the same current flowing in Q2, thus the circuit can copy, or ‘mirror’, a current from one part of a circuit to another. Iin Icopy Q 6 Q 7 Fig.3. The basic matched-transistor current mirror. Transistors with identical characteristics and environment are referred to as ‘matched’. They are often used in IC designs, where designers can use layout techniques to ensure the transistors are closely matched. For discrete designs, matched transistors in a single package are available. In the circuit in Fig.3, Q6 is ‘diode connected’ – the base and collector are shorted so the transistor acts as a diode (the base-emitter junction). It is easy to establish a fixed current in Q6 by connecting the collector to a fixed voltage via a resistor – exactly as in Fig.1, where the collector of Q6 is connected to the supply via R2. This will fix the VBE of Q6 and Q7 and cause a fixed current to flow in Q7 (Iout). Thus, Q7 acts like a constant-current source with one end connected to ground. As just discussed, Q6 and R2 provides the reference VBE to set the current in Q7. Within reason, we can connect more transistors in the same way and get further copies of the reference current in Q6. This is done in the circuit in Fig.1 – Q8 provides a second copy of the reference current. Transistors can only be added ‘within reason’ because each diverts more base current from the reference and makes it more difficult to ensure they are all matched. Differential amplifier When investigating a circuit with multiple blocks it can be useful to simulate individual sections. The circuit for an LTspice simulation of just a basic differential amplifier is shown in Fig.4, this uses resistors instead of an active load to make it simpler (R1 and R2 in Fig.4 instead of Q3 and Q4 in Fig.1). Similarly, the bias is provided by an ideal current source rather than the circuit implementation in Fig.1. The circuit uses a ±15 V split power supply (V3 and V4, to provide an illustration of this in LTspice, in contrast to the signal supply of Fig.1 (LTspice version shown later). The supply lines are VCC and −VEE (labelled as nVEE). The input signal has 0V common mode as this is the middle point of the split supply. The circuit in Fig.4 uses a custom transistor model (myNPN) based on the default LTspice NPN model. Only two parameters are changed the saturation current (IS) and the Forward Early voltage (VAF). The default is IS = 1.0 × 10−16A, but using 1.0 × 10−14A brings the value closer to typical signal transistors. The key effect is to scale the base-emitter voltage to emitter current relationship, shifting the VBE for a given collector current. We will look at Early voltage later. Notice the symmetry of the differential amplifier – it is key to its operation Practical Electronics | September | 2020 Fig.4- Basic differential amplifier LTspice schematic. – to achieve it the two transistors must be matched. It has two inputs (B1 and B2 on Fig.4) and two outputs (C1 and C2, also on Fig.4). Small differences in the input voltages cause relatively large changes in the output voltages, also in a differential manner (ie, as one output voltage increases, the other will decrease by the same amount). We can, however, choose to use only one output (‘single-ended’ output). Key points to understanding the circuit’s operation are: first, a transistor’s collector and emitter currents are very sensitive to changes in base voltage; and second, the emitters are connected to a constantcurrent source (IE). The constant-current source means that the sum of the two emitter currents must always be equal to IE. If the two base voltages are equal, and the transistors are exactly the same then it follows that IE will split equally between the two transistors; that is, they will draw the same base current, and their collector currents will be equal. Since the two collector resistors are equal the voltages dropped across them will also be equal (assuming there is no output current). If the two input voltages change together (a common-mode input signal) then the symmetry will not be disturbed, IE will still split equally between the two transistors. At first, though, it may seem that changing the input voltage must change the collector and emitter currents, but it does not have to because the emitter voltage is free to change, whereas IE is fixed by virtue of the constant-current source. The lack of response to commonmode inputs helps makes the design of very high-gain DC amplifiers possible. If the temperature of a single-transistor amplifier changes then the bias currents and voltages shift. In capacitively coupled (ie, AC) circuits this does not matter because the temperature changes are slow and are below the cut-off frequency due to the coupling capacitor. However, if there is no capacitive coupling then any changes in voltages due to temperature (or other forms of ‘drift’) are effectively indistinguishable from required lowfrequency signals and will be amplified. If the temperature of a properly matched differential pair changes, however, both transistors are affected equally and there is no change in the output (the drift is a common-mode signal). The worst place to get drift is in the first stage, as the error is amplified by all subsequent stages; thus, having a differential pair as the first stage is a good way of reducing overall drift. If we change the (still equal) input voltages by a large amount, then the circuit will cease to function as just described. For example, if we take the input voltages down to near the −VEE rail then the current source may no longer function properly. This would determine the amplifier’s commonmode input range. The high sensitivity of the transistor’s collector and emitter currents to base voltage comes into play when we make the voltages at the two inputs slightly different. This breaks the symmetry and causes a larger proportion of IE to flow in one transistor than in another. For example, if we increase VB1 slightly and decrease VB2 by the same amount then a greater proportion of IE will flow in Q1 than Q2. This will cause the voltage drop across R1 to be larger than that across R2, so VC1 will be lower than VC2. In op amp terminology, if we take a single-ended output from C2 then VB2 will act as the inverting input and VB1 as the non-inverting input. DC Sweep Fig.5. Plot of output voltages at the collectors vs input voltage difference (voltage between the bases) for the circuit in Fig.4. Practical Electronics | September | 2020 It is useful to look at the relationship between the input voltage difference (VB2 − VB1) and voltages at the two collectors over a range of DC values for the input. We can plot this using a DC sweep simulation in LTspice. To do this, select the DC sweep simulation command, select the source as V1, set sweep type to linear and select the range (start and stop voltages) and the increment value. The simulator will calculate DC voltages in the circuit for all values of the selected source starting at the start 45 Fig.6. Plot of differential input voltage (VB2 – VB1) and differential output voltage (VC2 – VC1) for the circuit in Fig.4. voltage, stepping by the increment until the stop voltage is reached. Stepping V1 by 1mV from −150mV to +150mV and plotting the voltages at C1 and C2 produces the result shown in Fig.5. Fig.5 shows that differences over a few tens of mV result in most of IE flowing in one or other of the two transistors. Over a large input difference range the response of the circuit is exponential, but in the range of a few mV difference between the inputs the change in the output voltage is nearenough directly proportional to the input difference (the central part of the curves in Fig.5 are straight). So, we have a linear differential amplifier for small input voltage differences. The voltage gain of the circuit in Fig.4 (difference-in to difference-out) is given by gmRC where RC is the collector resistor value (equal to both R1 and R2). g m is the transconductance gain of the transistor – the ratio of collector signal current (output) to base-emitter signal voltage (input). People are generally more familiar with β (or hfe) as the transistor gain – this is the current gain, but using transconductance is often more convenient when we are dealing with a voltage input. We often assume that β is fixed at 100 if we do not have more specific information, and indeed the default transistor model in LTspice uses this value. g m is more complex in that it varies with bias current, so we can’t assume a fixed value. Specifically, gm = ICQ/VT where ICQ is the bias or quiescent collector current and VT is the ‘thermal voltage’, a term which occurs in many semiconductor equations. V T varies with temperature but is about 26mV at 27°C – a commonly used default value in rough calculations (27°C is also LTspice’s default temperature). For the circuit in Fig.4, IC is IE/2 = 0.5mA, so gm = 0.0005/0.026 = 19.2mS (gm is current/ voltage which is 1/resistance, which is measured in siemens, symbol S). The gain is therefore 0.0192 × 15,000 = 288. Knowledge of the expected gain and the linear input range indicated by Fig.5 informs the choice of input signal amplitude for a transient simulation. 1mV is used in Fig.4. The result is shown in Fig.6 – the output amplitude is 270mV, so the gain (270) is close to our rough calculation. Fig.6 shows a plot of voltage differences – note the syntax for the waveform V(X,Y) is the voltage at X measured from Y. Such plots can be obtained by right-clicking on wire X and selecting ‘Mark Reference’ from the menu, then clicking on Y. The gm equation shows that the choice of bias current from the current source influences the gain of the circuit. Running the circuit at a higher bias current provides more gain but has other effects too. Power consumption will be higher at higher bias currents and a transistor’s base-emitter resistance is dependent on bias current. Increasing operating currents result in a proportional decrease in base-emitter resistance and hence reduced differential input resistance. This will need to be considered in a real design but will not affect the simulations discussed here as the inputs are driven by ideal voltage sources. Active load Fig.7. LTspice schematic for the first stage of the circuit in Fig.1. The gain of the circuit in Fig.4 can be increased by increasing the collector resistors as well as increasing the bias current; however, this also has its limiting factors. The output voltage with no signal present is VCC − RCIE/2, the supply minus the voltage dropped by the resistor with the bias current flowing through it. Increasing RC reduces this voltage, but it cannot go much below 0V or Q1 and Q2 will start to saturate (the emitters are at −VBE). This limits the maximum RC at a given bias current. Increasing VCC could compensate, but this is likely to be constrained by the requirements of other 46 Practical Electronics | September | 2020 Fig.8. Plot of differential input voltage (VB2 – VB1) and output voltage (Vout) for the circuit in Fig.7. circuitry, and realistically cannot be very large. The solution is to use an active load, as in the circuit in Fig.1, which has Q3 and Q4 in place of the collector resistors. Active loads allow bias currents to be set to any reasonable level while presenting an effective resistance value equal to the transistor’s output resistance, which can be as high as megaohms. Q3 and Q4 in Fig.1 form a current mirror like that in Fig.3, except using PNP transistors. Recall the discussion on the symmetry of the differential amplifier. If we assume that the current mirror is ideal, then with no differential signal present (equal base voltages for Q1 and Q2) the circuit’s balance is preserved. Q1’s and Q2’s collector currents are both IE/2. Q1’s collector current acts as the reference for the mirror and is copied from Q3 to Q4 where it exactly matches Q2’s collector current. However, if we apply a voltage difference, then Q1’s current copied to Q4 will not match the current in Q2. We cannot have two different currents in the same wire, so what happens? The answer is that the transistors are not perfect current sources and have some resistance between collector and emitter, referred to as their output resistance (ro). The difference between Q4’s and Q2’s collector currents will flow in their output resistances. The resistances of the two transistors are in parallel as far as this difference current is concerned, so the effective value is the parallel combination of Q2’s and Q4’s output resistance, which is ro/2, assuming they are matched. Comparing this with the gain formula for the circuit in Fig.1 indicates a Practical Electronics | September | 2020 possible gain of gmro/2 but the current delivered to the output is twice that of the circuit in Fig.4 because the current from Q1 is mirrored to the output (at C2), doubling the potential differential gain to g mr o. However, although the differential amplifier with active load is symmetrical in current terms, the diode-connected transistor Q3 presents a low resistance, so the voltage signal at C1 in Fig.1 is small. Therefore, we use the single-ended output from C2, which provides half the gain compared to differential output (if it were available), so the gain is gmro/2. Early voltage The value of a transistor’s output resistance depends on a parameter called the Early voltage (VA); specifically, ro = VA/ICQ where ICQ is the collector bias current. This is like the gm and baseemitter resistance discussed earlier in being dependent on bias current. The default value for V A in calculations is typically 100V, but for the default transistor models in LTspice it is infinite, so simulation results will not match expectations unless this is changed. Therefore, the Early voltage (V A F parameter) has been set to 100 in the simulations used here. The value of ro for the circuit in Fig.4 is 100/0.0005 = 200kΩ, which does not have much effect in parallel with RC of 15kΩ, but including it gives the gain as 268, which is closer to the simulation. Finally, we get to the simulation of the input stage of Fig.1. The LTspice schematic is shown in Fig.7. Here we have somewhat arbitrarily chosen a current of 200µA for the mirror reference (100µA bias each for Q1 and Q2), R2 is set using (VCC – VBE)/Iref = (10 – 0.6)/200µA = 47kΩ. With this bias current we get gm = 100µA/0.026 = 3.85mS and ro = 100/100µA = 1MΩ, so the gain is 1MΩ × 3.85mS/2 = 1923. Simulation results are shown in Fig.8. The simulated gain is about 1970. The gain of the circuit in Fig.7 is strongly dependent on the load resistance – driving a low resistance will dramatically reduce the gain. This is why an extremely high load resistance was used here. The output resistance is around 500kΩ, so setting R1 to this value will half the output voltage. The second stage in Fig.1 presents quite a low resistance load to the differential amplifier, so the gain from the input to Q2’s collector in circuit in Fig.1 will be much lower than the circuit in Fig.7. However, the second stage can add significant gain, so overall the circuit can have a higher gain than with just the single stage. Despite this, it can be argued that the circuit in Fig.1 wastes much of the potential gain from the differential amplifier, and many op amp designs use circuits with a much higher input resistance for the circuit directly after the differential stage. Simulation files Most, but not every month, LTSpice is used to support descriptions and analysis in Circuit Surgery. The examples and files are available for download from the PE website. 47