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Cheeky chiplets Techno Talk Max the Magnificent Instead of a single humongous silicon chip, tomorrow’s devices may involve multiple chiplets in the form of optical chiplets, libraries of chiplets, die-to-die (D2D) interconnect, and network on chip (NoC) technology. A chiplet-based future is closer than you think. I t’s not so long ago that the designers of digital integrated circuits (a.k.a. ‘silicon chips’ or just ‘chips’) employed the terms SSI, MSI, LSI, VLSI, and ULSI to represent Small-, Medium-, Large-, Very-Large-, and Ultra-Large-Scale Integration, respectively. By one convention, the number of primitive gates represented by these terms were: SSI (1-12), MSI (13-99), LSI (100-999), VLSI (1,000-999,999), and ULSI (1,000,000 or more). In order to ‘compare apples to apples,’ we also used to talk in terms of the number of ‘equivalent gates’ on a chip. Most designers – excluding those working with emitter-coupled logic (ECL) – adopted the convention that an equivalent gate was represented by a 2-input NAND gate, which equates to four transistors in a CMOS chip. I find it interesting that the huge number of gates and transistors that can be implemented on today’s chips has rendered such fine distinctions moot. As a result, terms suggesting greater than VLSI levels of integration are no longer in widespread use. How big? How many? In my previous Techno Talk column (PE, January 2024), we touched on the topic of ‘technology nodes’ (a.k.a. ‘process technologies,’ ‘process nodes,’ or just ‘nodes’), which refers to specific semiconductor manufacturing processes. One way to think about this is that the number associated with a process node represents the size of the smallest physical structure that can be created in or on the surface of the chip. Thus, a 1µm node can have features – like the width of tracks, for example – of one millionth of a meter in size. The smaller the features, the greater the number of transistors that can be squeezed into the same area. For example, Apple’s latest and greatest A17 Pro processor, which is implemented at the 3nm node (where 1nm is one billionth of a meter), boasts over 19 billion transistors (my eyes are watering just thinking about this number). The problem is that we are reaching the maximum physical size of chips 8 that can be constructed using today’s extreme ultraviolet (EUV) lithographic technologies. The practical limit is around 25mm × 25mm = 625mm2 (roughly a square inch). It is possible to create larger devices up to around 29mm × 29mm = 840mm2, but the yield (good chips vs. bad chips) quickly falls to unacceptable (unprofitable) levels. The ‘problem’ is that we have an insatiable desire for more and more transistors. Artificial intelligence (AI) and machine learning (ML) applications are sprouting like mushrooms. Also, they are migrating out of the cloud (in the form of data centers) to the Edge, which is where the internet meets the real world. So, what’s the solution? I’m glad you asked. The industry is currently buzzing with excitement over the latest developments in… Cheeky chiplets The technical term for a semiconductor chip is ‘die’ (plural ‘dice’). The solution to our capacity conundrum is to implement a large design across multiple dice, mount them on a common substrate (base), and present everything in a single package. In this case, the dice are commonly referred to as ‘chiplets’ or ‘tiles,’ the packaged product is referred to as a ‘multi-die system,’ and the substrate is typically a silicon interposer, although organic substrates (special printed circuit boards) are also a possibility. There are four main chiplet use cases. One is to scale things up by mounting multiple homogeneous (identical) chiplets (think multiple processing units) on the substrate. Another is to take a design that is too big to fit on a single die, and to split that design into two or more chiplets. A third use case is to take functions like transceivers that have already been proven at one technology node and implement them as chiplets that support the main die. The fourth scenario is to disaggregate everything into heterogeneous (dissimilar) dice, each being implemented at the best node (in terms of cost, power, and so on) for its function. Today’s chiplet outliers Until recently, the only companies using chiplet technology have been outliers like the folks at Intel who control every aspect of the fabrication process. In the case of Intel’s Agilex 7 FPGAs, for example, the main die is supported by two to six transceiver (XCVR) chiplets. Another Intel example is provided by their Data Center GPU Max Series of devices (these used to be known as Ponte Vecchio GPUs). These bodacious beauties boast 47 chiplets and 100+ billion transistors. ‘O-M-Goodness gracious me,’ is all I can say. Chiplets for the unwashed masses The way digital logic designers create today’s system-on-chip (SoC) devices is as a collection of ‘soft’ intellectual property (IP) blocks. Many of these IP blocks are provided by trusted third-party vendors because there’s no point in reinventing the wheel (in the form of a processor core or a USB interface, for example). The designers also create their own ‘secret sauce’ IPs that will differentiate this device from its competitors. These IPs are represented at the register transfer level (RTL) of abstraction, and all the IP descriptions are compiled (synthesised) into the final gate-level chip design. The dream is to be able to create tomorrow’s multi-die systems as a collection of ‘hard’ IP blocks in the form of chiplets. In this case, some chiplets would come from trusted third-party vendors while others would be developed in-house. If you’d asked me when this would come to be six months ago, I would have guessed it to be five or more years in our future. Since then, I’ve been talking to companies like Ayar Labs (optical interconnect chiplets), Arteris (network on chip (NoC) technology), YorChip and Zero ASIC (both offering libraries of chiplets), and Eliyan (die-to-die interconnect). I’m also looking forward to the forthcoming Chiplet Summit, which will be held 6-8 February 2024 at the Santa Clara Convention center. This will be the place for chiplet companies to ‘see and be seen.’ All I can say is that I now think our chiplet-based future is a lot closer than I’d previously thunk. Practical Electronics | February | 2024