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Circuit Surgery Regular clinic by Ian Bell Topics in digital signal processing – the sample-and-hold circuit and ADC Inputs W e are looking at various Fig.1. Generic DSP system structure. signal is commonly captured at Sampling switch the required sample times by a sample-and-hold circuit (as shown Vin A1 A2 Vout in Fig.1). The basic principle here Sampling CS capacitor is that for an ADC to perform a conversion it needs the analogue input voltage to be constant for a certain amount of time, which will Fig.2. Basic sample-and-hold circuit. depend on the implementation of the ADC. If the input voltage changes representation of the signal. Problems significantly during this time then errors can occur due to both inaccuracies in may occur in the conversion. The samplethe sample timing and value (voltage) and-hold block, which is usually part of the sampled signal. of the ADCs input circuit, performs A basic sample-and-hold circuit is this task. shown in Fig.2. As noted, this will often If the input signal changes very slowly be included on the ADC chip (or as part with respect to the ADC’s operating of a microcontroller’s ADC subsystem). speed, the voltage change may not be However, separate sample-and-hold significant, and the sample-and-hold chips are available. The performance circuit may not be needed. However, of a typical ADC will depend on the in many ADC applications expected characteristics of the built-in sampling changes in the input voltage will result circuit and its interaction with external in errors if there is no sample-andcircuitry; therefore, it helps to be aware hold circuit. For example, a successive of the process when using ADCs. The approximation converter (a common characteristics of the sampling circuit type of ADC) uses an internal digitalare usually covered in ADC datasheets. to-analogue converter (DAC) to compare The sampling circuit is essentially an analogue version of the digital output a switch and a capacitor, as seen in code with the input voltage. As the name Fig.2. The switch is electronic (eg, a suggests, it improves the accuracy of the MOSFET). In Fig.2, A1 is typically the digital code in successive steps using external circuitry driving the ADC. It the comparison to decide on each output may be an amplifier, but does not have bit in turn from most to least significant. to be, for example it could be a potential If the input voltage changes during the divider connected to the ADC’s input. conversion the partially complete digital Typically, A2 represents the input part code will not be compared to the same of the ADC’s conversion circuitry. In input value on each step, causing errors a separate sample-and-hold device, in the final result. A1 and A2 could be buffer amplifiers designed to provide high-performance operation. When the sampling switch Sample-and-hold is closed A1 directly drives CS, so the circuit characteristics voltage on CS will follow vin – that is, As with any circuity, the sampling it will track changes in v in. For this process may be subject to non-ideal characteristics, which in this case reason, this circuit is also referred to can introduce errors into digitised as a ‘track and hold’. When the switch is closed the capacitor will retain Digital Analogue (hold) whatever voltage was on it at the instant the switch opened. Digital Reconstruction DAC Out processing filter The circuit in Fig.2 is idealised (assuming the components are ideal). In reality, we need to consider Practical Electronics | July | 2024 37 topics related to digital signal processing (DSP). DSP covers a wide range of electronics applications where signals are manipulated, analysed, generated, stored or displayed as digital data, but originate from, and/or are output as, real-world signals for interaction with humans or other parts of the physical world. Fig.1 shows the key elements of a generic DSP system with a signal path from an analogue input via digital processing to an analogue output. This does not necessarily represent every DSP system (not all have all the parts shown) but it serves as a useful reference for the various subsystems we will examine. In the previous two articles we looked at the fundamentals of sampling and the properties of ADCs. We covered the properties of sampled signals and discussed the Nyquist-Shannon theorem and aliasing. The theorem states that if the input does not contain any frequency components at or beyond half the sampling frequency (the Nyquist rate) then it is possible to perfectly reproduce the original signal from the sample data. The antialiasing filter shown in Fig.1 is used to remove the unwanted frequencies which may cause errors. ADCs can also introduce errors or noise in the sampled representation of the signal. Quantisation noise is caused by the finite number of values the ADC’s output codes can take (2N values for N bits) and occurs even with an ideal ADC. Real ADCs have a number of non-ideal characteristics, which we discussed last month, which can add additional errors. The discussion so far has not covered all aspects of the process of getting an analogue signal into digital form. The Analogue In Antialiasing filter Sample and hold ADC Sampling switch Vin A1 RS Leakage currents Sampling capacitor A2 Vout CS Fig.3. Sample-and-hold circuit with some non-ideal characteristics. additional parameters. There will be resistance (RS) between the source of the signal being sampled and the sample capacitor (see Fig.3). This, together with the sample capacitor, will influence how long it will take after the sample switch is closed for the capacitor to charge to the input voltage in order to obtain an accurate sample value. There will also be leakage currents which will change the voltage on the sample capacitor over time, limiting the time which the sample can be accurately held for. There may be other mechanisms causing potential errors in sampling circuits. For example, a MOSFET sampling switch can couple the control signal to, or inject charge into, the sampling capacitor. Sampling and holding simulation Fig.4 shows an LTspice circuit based on Fig.3. The sampling capacitor is C1 and the input series resistance is R1. The leakage current is modelled with the I1 current source, which is configured for the ideal case (zero current) in Fig.4. The switch is close to ideal (on resistances much smaller than R1, off resistance very large at 10MΩ). The switch is controlled by the 1V SamplePulse waveform from V3 (the switch threshold is 0.5V). This is simply a square wave which will put the circuit alternately into track and hold modes. The circuit values, signals and timing in the circuit in Fig.4 are to illustrate the principle of operation and are not related to any particular ADC or sampling system. The results from the simulation in Fig.4 are shown in Fig.5. The sampling waveform (cyan trace) has been scaled and shifted with a formula for convenience of showing alongside the signals and labelled with the track and hold conditions. The input waveform (green trace) is the sum of the two sinewaves from V1 and V2. The output waveform (red trace) can be seen to follow the input when the circuity is in track mode. The output is constant during the hold periods, with a value equal to the input at the start of the hold period. In a DSP system the ADC would perform conversions on the held signal. Fig.4. LTspice schematic to illustrate sampling onto a capacitor. Fig.6 shows a zoom in from Fig.5 on the first hold to track transition. This shows that the output voltage does not immediately equal the input voltage when the circuit enters track mode. The sampling capacitor has to charge (or discharge) from the previous hold voltage to the current input voltage. The time taken depends on the RC time constant and the amount of voltage change, and is referred to as the sample-and-hold’s ‘acquisition time’. After acquisition the output will follow the input unless the input changes too fast for the voltage on the capacitor to follow (again related to the time constant). Fig.7 shows the effect of leakage current. This uses the circuit in Fig.4 with the leakage current source I1 set to 1µA. Leakage current can flow via the sampling switch (noninfinite off resistance), into the next circuit stage (A2 in Fig.3) or via the capacitor’s imperfect dielectric insulation. Leakage results in a progressive change (droop) in the held voltage, as can be seen by comparing the waveforms in Fig.5 and Fig.7. Droop rate is the rate at which voltage on the sample capacitor changes during the hold interval. It is determined by IL/CS where IL is the leakage current, and CS is the sampling capacitance. Note that a constant leakage current results in a linear voltage change on the capacitor unlike the nonlinear change when charging through a resistor. Fig.5. Waveforms from the LTspice circuit in Fig.4 (I1 is zero). 38 Practical Electronics | July | 2024 Relating ADC and sample-and-hold circuit characteristics The performance of the sampling process depends on both the sample-and-hold circuit and the ADC. If the sampling is of insufficient capability compared with the ADC then it may undermine the quality of the digitised signal. Two key ADC parameters, which we discussed last month, are the conversion time and the LSB. We will briefly recap these. The ‘conversion time’ (tC) is how long it takes from a conversion being initiated and the data becoming available. If conversions Digital Signal Processing Topics – Sample-and-hold Circuit and ADC Inputs are performed continuously the Fig.6. Zoom in on waveforms in Fig.5 to show signal acquisition on the sampling capacitor. conversions time indicates the maximum number of conversions %) 𝑡𝑡!"#N=is𝑅𝑅$the 𝐶𝐶$ ln(2 per second that can be performed (sample Sample-and-hold circuit timing Here, number of ADC bits. This rate). In the simplest case, sample rate is an application of the standard RC Fig.8 shows characteristics of the will be 1/tC, but it is not always that charge/discharge equation: sampling process. The sampling switch is controlled by the sampling clock, which simple. Some converters (eg, pipelined 𝑉𝑉&'()* instructs the sample-and-hold circuit to ADCs) have a faster sample rate than 1/tC 𝑡𝑡 = 𝑅𝑅𝑅𝑅 ln * , 𝑉𝑉'('+')* change between the sample (track) and because processing of multiple step-byhold modes. When the switch is closed, step conversions occurs simultaneously. sampling begins and the capacitor will In such cases there is a latency of several where the ratio of final to initial voltage is charge to the input voltage, this takes the worst case – the entire 𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟 (2N). a finite time – the time required by the ADC𝐿𝐿𝐿𝐿𝐿𝐿 input = range 2% voltage sample-and-hold circuit to acquire the Once the input tACQ td sample value. The more accurately you has been acquired, the need the capacitor voltage to match the sample-and-hold circuit Input input voltage the longer you have to wait can enter the hold state tJ 𝑑𝑑𝑣𝑣 Sample '(conversion to (all other things being equal). to allow 𝑡𝑡, ≤ 𝐿𝐿𝐿𝐿𝐿𝐿 𝑑𝑑𝑑𝑑 Again, this is We can define the ‘acquisition time’ take place. State Track sample Hold Hold (tACQ) as the duration from the end of controlled by the sampling clock. The relevant clock the hold state (sampling begins) and the Clock edge represents the time at point at which the voltage on the 𝑣𝑣'( = 𝐴𝐴 command 𝑠𝑠𝑠𝑠𝑠𝑠( 2𝜋𝜋𝜋𝜋𝜋𝜋)to hold Sample Hold which the sampling capacitor settles to within 1 acquired achieved is given. The circuit will take LSB of the input voltage. With reference ing Topics to – Sample-and-hold and ADC Inputs Sampling Hold a finite time to actually enter Fig.3 and Fig.8,Circuit acquisition time is started Requested the hold state (and hence then given by: 𝑑𝑑𝑣𝑣 '( the sample). This is take = 2𝜋𝜋𝜋𝜋𝜋𝜋 𝑐𝑐𝑐𝑐𝑐𝑐( 2𝜋𝜋𝜋𝜋𝜋𝜋) 𝑡𝑡!"# = 𝑅𝑅$ 𝐶𝐶$ ln(2% ) 𝑑𝑑𝑑𝑑 called ‘aperture delay’ (tAD). Fig.8. Sample-and-hold circuit timing characteristics. Fig.7. Waveforms from the 𝑉𝑉&'()* 𝑡𝑡 = 𝑅𝑅𝑅𝑅 ln * , LTspice 𝑉𝑉'('+')* circuit in Fig.4 (I1 is 1µA). 𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟 𝐿𝐿𝐿𝐿𝐿𝐿 = 2% 𝑡𝑡, 𝑑𝑑𝑣𝑣'( ≤ 𝐿𝐿𝐿𝐿𝐿𝐿 𝑑𝑑𝑑𝑑 𝑑𝑑𝑉𝑉'( 𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟 𝑡𝑡 < 𝑑𝑑𝑑𝑑 2% 2𝐴𝐴𝐴𝐴𝐴𝐴𝑡𝑡- < 𝑡𝑡- < 2𝐴𝐴 2% 1 2% 𝜋𝜋𝜋𝜋 𝑣𝑣'( = 𝐴𝐴 𝑠𝑠𝑠𝑠𝑠𝑠( 2𝜋𝜋𝜋𝜋𝜋𝜋) 𝑑𝑑𝑣𝑣 Practical Electronics | July | 2024 '( = 2𝜋𝜋𝜋𝜋𝜋𝜋 𝑐𝑐𝑐𝑐𝑐𝑐( 2𝜋𝜋𝜋𝜋𝜋𝜋) 𝑑𝑑𝑑𝑑 39 ADC input voltage ADC input voltage ΔV ΔV Δt V2 Δt V2 Sample held Input level reacquired V1 V1 tC tC Conversion time Conversion time g Topics – Sample-and-hold Circuit and ADC Inputs 𝑡𝑡!"# = 𝑅𝑅$ 𝐶𝐶$ ln(2% ) Conversion starts Conversion finishes Fig.9. Changing input signal to an ADC without a sample-andhold circuit. 𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟 2% Time Fig.10. ADC input with sample-and-hold circuit for comparison with Fig.9. conversion cycles before the result of a particular conversion 𝑉𝑉&'()* 𝑡𝑡is=available. 𝑅𝑅𝑅𝑅 ln * , 𝑉𝑉'('+')* The least-significant bit (LSB) is the input change that the ADC can resolve, that is the smallest input change required for a change in code output. Last month, we saw that: 𝐿𝐿𝐿𝐿𝐿𝐿 = Conversion finishes Conversion starts Time Sample and hold input voltage ΔV Δt V2 where the ADC’s input range is defined as VRefH – VRefL, the difference between the upper and lower reference voltages. N – Sample-and-hold V1 Digital Signal Processing Topics Circuit and ADC Inputs is the of bits. LSB and conversion time can be related 𝑑𝑑𝑣𝑣number '( tJ ≤ 𝐿𝐿𝐿𝐿𝐿𝐿 to𝑡𝑡,sample-and-hold circuit parameters – faster conversion and Aperture 𝑑𝑑𝑑𝑑 jitter time more bits (smaller LSB) generally require higher performance 𝑡𝑡 %) !"# = 𝑅𝑅$ 𝐶𝐶$ ln(2 sampling circuits. need for sample-and-hold circuits 𝑣𝑣The '( = 𝐴𝐴 𝑠𝑠𝑠𝑠𝑠𝑠( 2𝜋𝜋𝜋𝜋𝜋𝜋) Fig.9 shows a graph of input voltage against time for an ADC for which there is no sample-and-hold circuit. We assume the conversion takes time tC, during which the input changes from V1 to V2. If this change (V2 – V1) is larger than one LSB 𝑑𝑑𝑣𝑣'( = 2𝜋𝜋𝜋𝜋𝜋𝜋 2𝜋𝜋𝜋𝜋𝜋𝜋) may be disrupted. Fig.10 shows the then the 𝑐𝑐𝑐𝑐𝑐𝑐( conversion 𝑑𝑑𝑑𝑑 same situation with a sample-and-hold circuit (similar to Fig.6) for comparison. For a changing input voltage, the possibility of error depends on the relationship between the rate of change of voltage and 𝑑𝑑𝑉𝑉'( 𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟 𝑡𝑡- < the conversion time. The rate of change of input voltage is 𝑑𝑑𝑑𝑑 2% the voltage difference ΔV divided by the time taken for that change Δt (ie, rate = ΔV/Δt), as shown in Fig.9. The symbol Δ (delta) means ‘change of’. Measuring the rate as shown on Fig.9 is fine2𝐴𝐴 for a constant rate of change, but for real signals, 2𝐴𝐴𝐴𝐴𝐴𝐴𝑡𝑡the where changes constantly, we use the calculus form - <rate 2% 𝑡𝑡- < 1 2% 𝜋𝜋𝜋𝜋 Sample should be held at this time Sample actually held at this time Time 𝑉𝑉&'()* 𝑡𝑡 = 𝑅𝑅𝑅𝑅 ln * , 𝑉𝑉'('+')* Fig.11. Aperture Jitter timing. given by: rate = dV/dt, which simply implies measurement of the rate over an infinitely short time interval. 𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟 𝐿𝐿𝐿𝐿𝐿𝐿 If we=multiply the maximum rate of change of a signal by 2% the conversion time we can find the largest amount the input signal changes during this time, which must be less than the LSB to prevent errors. We can write this mathematically as: 𝑡𝑡, 𝑑𝑑𝑣𝑣'( ≤ 𝐿𝐿𝐿𝐿𝐿𝐿 𝑑𝑑𝑑𝑑 An obvious question at this point is how we know what rate of change value to use. We should probably look at the most 𝑣𝑣'( = 𝐴𝐴 𝑠𝑠𝑠𝑠𝑠𝑠( 2𝜋𝜋𝜋𝜋𝜋𝜋) 𝑑𝑑𝑣𝑣'( = 2𝜋𝜋𝜋𝜋𝜋𝜋 𝑐𝑐𝑐𝑐𝑐𝑐( 2𝜋𝜋𝜋𝜋𝜋𝜋) 𝑑𝑑𝑑𝑑 Fig.12. Circuit for AD4000 ADC simulation in LTspice. 𝑑𝑑𝑉𝑉'( 𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟 𝑡𝑡 < 𝑑𝑑𝑑𝑑 2% 2𝐴𝐴𝐴𝐴𝐴𝐴𝑡𝑡- < 40 𝑡𝑡- < 1 % 2𝐴𝐴 2% Practical Electronics | July | 2024 𝐿𝐿𝐿𝐿𝐿𝐿 = 𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟 2% 𝑑𝑑𝑣𝑣'( 𝑡𝑡, ≤ 𝐿𝐿𝐿𝐿𝐿𝐿 𝑑𝑑𝑑𝑑 demanding case and one way to do this to consider a sinewave at the highest 𝑑𝑑𝑣𝑣'( frequency present in the input signal. Our input ≤ 𝐿𝐿𝐿𝐿𝐿𝐿 , can be 𝑡𝑡written: 𝑑𝑑𝑑𝑑 𝑣𝑣'( = 𝐴𝐴 𝑠𝑠𝑠𝑠𝑠𝑠( 2𝜋𝜋𝜋𝜋𝜋𝜋) where f is the frequency in hertz and A is the amplitude (peak). the2𝜋𝜋𝜋𝜋𝜋𝜋) rate of change we use calculus to differentiate 𝑣𝑣'(To = find 𝐴𝐴 𝑠𝑠𝑠𝑠𝑠𝑠( the signal function (find dv in/dt). Readers familiar with 𝑑𝑑𝑣𝑣'( calculus will know that differentiating a sine function gives = 2𝜋𝜋𝜋𝜋𝜋𝜋 𝑐𝑐𝑐𝑐𝑐𝑐( 2𝜋𝜋𝜋𝜋𝜋𝜋) 𝑑𝑑𝑑𝑑 a cosine function; so we get: 𝑑𝑑𝑣𝑣'( = 2𝜋𝜋𝜋𝜋𝜋𝜋 𝑐𝑐𝑐𝑐𝑐𝑐( 2𝜋𝜋𝜋𝜋𝜋𝜋) 𝑑𝑑𝑑𝑑 𝑑𝑑𝑉𝑉'( 𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟 The maximum value of a cosine function is 1, so the maximum 𝑡𝑡- < % 𝑑𝑑𝑑𝑑 rate of change2is 2πfA. We can use this figure in the calculation given𝑑𝑑𝑉𝑉 above to𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟 determine if a sample-and-hold circuit is '( 𝑡𝑡- < may required. This 𝑑𝑑𝑑𝑑 2% not seem like a major issue as most ADCs will have the sampling system anyway; however, the same 2𝐴𝐴 2𝐴𝐴𝐴𝐴𝐴𝐴𝑡𝑡- < % 2 Fig.13. Results 2𝐴𝐴 from circuit 2𝐴𝐴𝐴𝐴𝐴𝐴𝑡𝑡- < % 2 in Fig.12. 1 𝑡𝑡- < % 2 𝜋𝜋𝜋𝜋 𝑡𝑡- < Simulation files Most, but not every month, LTSpice is used to support descriptions and analysis in Circuit Surgery. The examples and files are available for download from the PE website: https://bit.ly/pe-downloads approach can also be used with other converter timing issues as we shall see shortly. Furthermore, an understanding of the behaviour of the sampling process is useful when working with ADCs, for example it helps to know that if you drive an ADC’s input from a source (eg, a sensor) with a high internal resistance then that resistance will increase the acquisition time, which may cause errors. Jitter DSP systems typically have a constant frequency sample clock, rather than taking samples at arbitrary times (eg, one-off 1 2% 𝜋𝜋𝜋𝜋 Fig.14. Results from circuit in Fig.12 with R1 changed to 10kΩ. Practical Electronics | July | 2024 41 Digital Signal Processing Topics – Sample-and-hold Circuit and ADC Inputs measurements controlled by a user). In %) such in the aperture 𝑡𝑡!"# cases = 𝑅𝑅$ 𝐶𝐶$variations ln(2 Digital Signal Processing Topics – Sample-and-hold Circuit and ADC Inputs delay between Circuit clock cycles, or Inputs in the Digital Signal Processing Topics – Sample-and-hold and ADC clock edge timing itself, will cause a change in effective sample time in each %) 𝑡𝑡!"# = 𝑅𝑅$This 𝐶𝐶$ ln(2 cycle. is referred to as ‘aperture % 𝑉𝑉&'()*) 𝑡𝑡!"# = 𝑅𝑅$ 𝐶𝐶$ ln(2 𝑡𝑡 = 𝑅𝑅𝑅𝑅 * term, ‘clock jitter’ is used jitter’ (tJ)lnThe 𝑉𝑉'('+')* to refer to timing variations specifically in clock signals. 𝑉𝑉&'()*at the wrong time point www.poscope.com/epe Sampling 𝑡𝑡 = 𝑅𝑅𝑅𝑅 ln * 𝑉𝑉&'()* , 𝑉𝑉 means that the 𝑡𝑡 = 𝑅𝑅𝑅𝑅 ln *'('+')* , wrong voltage will 𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟 𝑉𝑉 𝐿𝐿𝐿𝐿𝐿𝐿 = '('+')* be converted. The voltage deviation 2% resulting from aperture jitter will show up as noise in the sampled signal. The 𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟 problem gets worse for higher input 𝐿𝐿𝐿𝐿𝐿𝐿 = 𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟 2% 𝐿𝐿𝐿𝐿𝐿𝐿 𝑑𝑑𝑣𝑣 =frequencies signal because the signal '( 2% 𝑡𝑡, will ≤ 𝐿𝐿𝐿𝐿𝐿𝐿 voltage change more in the jitter 𝑑𝑑𝑑𝑑 time. Thus, aperture jitter is a critical characteristic in ADCs used for high𝑑𝑑𝑣𝑣'( frequency signals. 𝑡𝑡, 𝑑𝑑𝑣𝑣'(≤ 𝐿𝐿𝐿𝐿𝐿𝐿 𝑑𝑑𝑑𝑑order 𝑡𝑡𝑣𝑣In ≤ 𝐿𝐿𝐿𝐿𝐿𝐿 for the aperture jitter of the , = '( 𝑑𝑑𝑑𝑑 𝐴𝐴 𝑠𝑠𝑠𝑠𝑠𝑠( 2𝜋𝜋𝜋𝜋𝜋𝜋) sample-and-hold circuit not to cause conversion errors the change in signal voltage (Vin) during the jitter time (tJ) must 𝑣𝑣'(be=less 𝐴𝐴 𝑠𝑠𝑠𝑠𝑠𝑠( 2𝜋𝜋𝜋𝜋𝜋𝜋) than the LSB. This is similar to 𝑑𝑑𝑣𝑣 𝑣𝑣'('( = 𝐴𝐴 𝑠𝑠𝑠𝑠𝑠𝑠( 2𝜋𝜋𝜋𝜋𝜋𝜋) 2𝜋𝜋𝜋𝜋𝜋𝜋 𝑐𝑐𝑐𝑐𝑐𝑐( 2𝜋𝜋𝜋𝜋𝜋𝜋) earlier about the the = problem discussed 𝑑𝑑𝑑𝑑 need for a sample-and-hold circuit (see Fig.11), except now we use aperture jitter 𝑑𝑑𝑣𝑣'( rather than conversion time, so we need: - USB - PWM 𝑑𝑑𝑣𝑣 = 2𝜋𝜋𝜋𝜋𝜋𝜋 𝑐𝑐𝑐𝑐𝑐𝑐( 2𝜋𝜋𝜋𝜋𝜋𝜋) - Ethernet 𝑑𝑑𝑑𝑑 '( = 2𝜋𝜋𝜋𝜋𝜋𝜋 𝑐𝑐𝑐𝑐𝑐𝑐( 2𝜋𝜋𝜋𝜋𝜋𝜋) - Encoders - Web server 𝑑𝑑𝑑𝑑 𝑑𝑑𝑉𝑉'( 𝑡𝑡 < 𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟 - LCD - Modbus 𝑑𝑑𝑑𝑑 2% - Analog inputs - CNC (Mach3/4) - IO - Compact PLC - up to 256 - up to 32 microsteps microsteps - 50 V / 6 A - 30 V / 2.5 A - USB configuration - Isolated PoScope Mega1+ PoScope Mega50 - up to 50MS/s - resolution up to 12bit - Lowest power consumption - Smallest and lightest - 7 in 1: Oscilloscope, FFT, X/Y, Recorder, Logic Analyzer, Protocol decoder, Signal generator 42 For a sinewave with a peak value A 𝑑𝑑𝑉𝑉 '( equal to 𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟 half the ADC range (the peak𝑑𝑑𝑉𝑉 𝑡𝑡 < 𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟 𝑑𝑑𝑑𝑑 '(-𝑡𝑡- < 2% to-peak sinewave 2𝐴𝐴 covers the entire input % 𝑑𝑑𝑑𝑑 2𝐴𝐴𝐴𝐴𝐴𝐴𝑡𝑡 2 < % = 2A) we have, using range, ie, -range 2 the maximum rate of change of sinewave calculated above, the following: 2𝐴𝐴 2𝐴𝐴𝐴𝐴𝐴𝐴𝑡𝑡- < 2𝐴𝐴 2𝐴𝐴𝐴𝐴𝐴𝐴𝑡𝑡- <2% 1% 𝑡𝑡- < %2 2 𝜋𝜋𝜋𝜋 So 1 𝑡𝑡- < % 1 2 𝜋𝜋𝜋𝜋 𝑡𝑡- < % 2 𝜋𝜋𝜋𝜋 For example, CD audio uses 16 bits at a sample rate of 44.1kHz. This means the highest input frequency must be limited to below 22.05kHz (if we a have perfect anti-aliasing filter). This is a requirement of sampling theory discussed previously – the highest frequency present in the input must be less than half the sampling frequency otherwise aliasing will occur in the sampled data. The above formula indicates a maximum aperture jitter of 220ps (picoseconds) and illustrates that aperture jitter requirements can be quite demanding. A sample rate of 44.1kHz is around one sample every 23μs – about one hundred thousand times longer than the indicated maximum aperture jitter time. However, the above calculation is probably somewhat pessimistic about the aperture jitter requirements as most of the content of a real audio signal will be at lower frequencies and any higher frequencies present will generally not be near maximum amplitude. ADC simulation So far we have not looked at an LTspice simulation of an ADC, however, there are models of several ADCs included in the downloaded library. These models have analogue outputs which represent the quantised signal – they do not provide the digital bits. This is because LTspice is not aimed at modelling digital (or mixed analogue and digital) systems, so providing many digital outputs for the code would not be particularly useful. Some digital signals are modelled, for example the start convert control input. The models focus on the input section and allow aspects such as the impact of the input circuit on the acquisition to be investigated. Noise and FFT simulations can also be performed. Fig.12 is similar to the example circuit for the AD4000 provided by Analogue Devices. The AD4000 is a 16-bit 2 MSPS, Precision, Pseudo Differential, successive approximation register ADC. The simulation circuit includes the device power supply (1.8V) and reference voltage (5V). Conversion is started by a rising edge on the CNV input, which is driven by a pulse waveform in the simulation. The input is a sinewave configured to exceed the reference voltage. The AD4000 has input overvoltage protection – not all ADCs do, so make sure that you are aware of the maximum ratings of any device you are using. The results from Fig.12 are shown in Fig.13. We see the output update after each conversion start pulse and we can see the quantisation of the output (red trace is stepped). When the input (green trace) exceeds the reference voltage the output remains at the maximum output value. The drive and ADC input voltages are equal, which indicates there is no significant interaction between the ADC input and external circuitry. Fig.14 shows the results with the input resistor changed to 10kΩ. Here we see the ADC input is not the same as the drive voltage from the V1 source – the input voltage changes as the ADC’s sampling switches change state. This is a simple example but illustrates how the ADC model can help evaluate the driver circuit providing input to the ADC. Introduction to LTspice Want to learn the basics of LTspice? Ian Bell wrote an excellent series of Circuit Surgery articles to get you up and running, see PE October 2018 to January 2019, and July/August 2020. All issues are available in print and PDF from the PE website: https://bit.ly/pe-backissues Practical Electronics | July | 2024