Silicon ChipCircuit Surgery - November 2024 SILICON CHIP
  1. Contents
  2. Publisher's Letter: The challenges of making electronics work worldwide
  3. Feature: The Fox Report by Barry Fox
  4. Feature: Net Work by Alan Winstanley
  5. Project: Ideal Diode Bridge Rectifiers by Phil Prosser
  6. Feature: Practically Speaking by Jake Rothman
  7. Back Issues
  8. Feature: Max’s Cool Beans by Max the Magnificent
  9. Project: Multi-Channel Volume Control, part one by Nicholas Vinen
  10. Feature: Teach-In 2024 – Learn electronics with the ESP32 by Mike Tooley
  11. Feature: Techno Talk by Max the Magnificent
  12. Project: Coin Cell Emulator by Tim Blythman
  13. Feature: Circuit Surgery by Ian Bell
  14. Review: MG4 XPower electric vehicle by Julian Edgar
  15. Subscriptions
  16. Feature: 14-segment, 4-digit LED Display Modules by Jim Rowe
  17. PartShop
  18. Advertising Index
  19. Market Centre
  20. Back Issues

This is only a preview of the November 2024 issue of Practical Electronics.

You can view 0 of the 80 pages in the full issue.

Articles in this series:
  • The Fox Report (July 2024)
  • The Fox Report (September 2024)
  • The Fox Report (October 2024)
  • The Fox Report (November 2024)
  • The Fox Report (December 2024)
  • The Fox Report (January 2025)
  • The Fox Report (February 2025)
  • The Fox Report (March 2025)
  • The Fox Report (April 2025)
  • The Fox Report (May 2025)
Articles in this series:
  • Win a Microchip Explorer 8 Development Kit (April 2024)
  • Net Work (May 2024)
  • Net Work (June 2024)
  • Net Work (July 2024)
  • Net Work (August 2024)
  • Net Work (September 2024)
  • Net Work (October 2024)
  • Net Work (November 2024)
  • Net Work (December 2024)
  • Net Work (January 2025)
  • Net Work (February 2025)
  • Net Work (March 2025)
  • Net Work (April 2025)
Articles in this series:
  • Practically Speaking (November 2024)
  • Practically Speaking (February 2025)
Articles in this series:
  • Max’s Cool Beans (April 2024)
  • Max’s Cool Beans (May 2024)
  • Max’s Cool Beans (June 2024)
  • Max’s Cool Beans (July 2024)
  • Max’s Cool Beans (August 2024)
  • Max’s Cool Beans (September 2024)
  • Max’s Cool Beans (October 2024)
  • Max’s Cool Beans (November 2024)
  • Max’s Cool Beans (December 2024)
Items relevant to "Multi-Channel Volume Control, part one":
  • Multi-channel Volume Control volume PCB [01111221] (AUD $5.00)
  • Multi-channel Volume Control control PCB [01111222] (AUD $5.00)
  • Multi-channel Volume Control OLED PCB [01111223] (AUD $3.00)
  • PIC16F18146-I/SO programmed for the Multi-Channel Volume Control [0111122B.HEX] (Programmed Microcontroller, AUD $10.00)
  • PIC16F15224-I/SL programmed for the Multi-Channel Volume Control [0111122C.HEX] (Programmed Microcontroller, AUD $10.00)
  • Pulse-type rotary encoder with pushbutton and 18t spline shaft (Component, AUD $3.00)
  • 0.96in cyan OLED with SSD1306 controller (Component, AUD $10.00)
  • 2.8-inch TFT Touchscreen LCD module with SD card socket (Component, AUD $25.00)
  • Multi-channel Volume Control control module kit (Component, AUD $50.00)
  • Multi-channel Volume Control volume module kit (Component, AUD $55.00)
  • Multi-channel Volume Control OLED module kit (Component, AUD $25.00)
  • Firmware (C and HEX) files for the Multi-Channel Volume Control (Software, Free)
  • Multi-channel Volume Control PCB patterns (PDF download) [01111221-3] (Free)
Articles in this series:
  • Multi-Channel Volume Control, Pt1 (December 2023)
  • Multi-Channel Volume Control Part 2 (January 2024)
  • Multi-Channel Volume Control, part one (November 2024)
  • Multi-Channel Volume Control, Part 2 (December 2024)
Articles in this series:
  • Teach-In 2024 (April 2024)
  • Teach-In 2024 (May 2024)
  • Teach-In 2024 – Learn electronics with the ESP32 (June 2024)
  • Teach-In 2024 – Learn electronics with the ESP32 (July 2024)
  • Teach-In 2024 – Learn electronics with the ESP32 (August 2024)
  • Teach-In 2024 – Learn electronics with the ESP32 (September 2024)
  • Teach-In 2024 – Learn electronics with the ESP32 (October 2024)
  • Teach-In 2024 – Learn electronics with the ESP32 (November 2024)
Articles in this series:
  • (November 2020)
  • Techno Talk (December 2020)
  • Techno Talk (January 2021)
  • Techno Talk (February 2021)
  • Techno Talk (March 2021)
  • Techno Talk (April 2021)
  • Techno Talk (May 2021)
  • Techno Talk (June 2021)
  • Techno Talk (July 2021)
  • Techno Talk (August 2021)
  • Techno Talk (September 2021)
  • Techno Talk (October 2021)
  • Techno Talk (November 2021)
  • Techno Talk (December 2021)
  • Communing with nature (January 2022)
  • Should we be worried? (February 2022)
  • How resilient is your lifeline? (March 2022)
  • Go eco, get ethical! (April 2022)
  • From nano to bio (May 2022)
  • Positivity follows the gloom (June 2022)
  • Mixed menu (July 2022)
  • Time for a total rethink? (August 2022)
  • What’s in a name? (September 2022)
  • Forget leaves on the line! (October 2022)
  • Giant Boost for Batteries (December 2022)
  • Raudive Voices Revisited (January 2023)
  • A thousand words (February 2023)
  • It’s handover time (March 2023)
  • AI, Robots, Horticulture and Agriculture (April 2023)
  • Prophecy can be perplexing (May 2023)
  • Technology comes in different shapes and sizes (June 2023)
  • AI and robots – what could possibly go wrong? (July 2023)
  • How long until we’re all out of work? (August 2023)
  • We both have truths, are mine the same as yours? (September 2023)
  • Holy Spheres, Batman! (October 2023)
  • Where’s my pneumatic car? (November 2023)
  • Good grief! (December 2023)
  • Cheeky chiplets (January 2024)
  • Cheeky chiplets (February 2024)
  • The Wibbly-Wobbly World of Quantum (March 2024)
  • Techno Talk - Wait! What? Really? (April 2024)
  • Techno Talk - One step closer to a dystopian abyss? (May 2024)
  • Techno Talk - Program that! (June 2024)
  • Techno Talk (July 2024)
  • Techno Talk - That makes so much sense! (August 2024)
  • Techno Talk - I don’t want to be a Norbert... (September 2024)
  • Techno Talk - Sticking the landing (October 2024)
  • Techno Talk (November 2024)
  • Techno Talk (December 2024)
  • Techno Talk (January 2025)
  • Techno Talk (February 2025)
  • Techno Talk (March 2025)
  • Techno Talk (April 2025)
  • Techno Talk (May 2025)
  • Techno Talk (June 2025)
Articles in this series:
  • Circuit Surgery (April 2024)
  • STEWART OF READING (April 2024)
  • Circuit Surgery (May 2024)
  • Circuit Surgery (June 2024)
  • Circuit Surgery (July 2024)
  • Circuit Surgery (August 2024)
  • Circuit Surgery (September 2024)
  • Circuit Surgery (October 2024)
  • Circuit Surgery (November 2024)
  • Circuit Surgery (December 2024)
  • Circuit Surgery (January 2025)
  • Circuit Surgery (February 2025)
  • Circuit Surgery (March 2025)
  • Circuit Surgery (April 2025)
  • Circuit Surgery (May 2025)
  • Circuit Surgery (June 2025)
Articles in this series:
  • El Cheapo Modules From Asia - Part 1 (October 2016)
  • El Cheapo Modules From Asia - Part 2 (December 2016)
  • El Cheapo Modules From Asia - Part 3 (January 2017)
  • El Cheapo Modules from Asia - Part 4 (February 2017)
  • El Cheapo Modules, Part 5: LCD module with I²C (March 2017)
  • El Cheapo Modules, Part 6: Direct Digital Synthesiser (April 2017)
  • El Cheapo Modules, Part 7: LED Matrix displays (June 2017)
  • El Cheapo Modules: Li-ion & LiPo Chargers (August 2017)
  • El Cheapo modules Part 9: AD9850 DDS module (September 2017)
  • El Cheapo Modules Part 10: GPS receivers (October 2017)
  • El Cheapo Modules 11: Pressure/Temperature Sensors (December 2017)
  • El Cheapo Modules 12: 2.4GHz Wireless Data Modules (January 2018)
  • El Cheapo Modules 13: sensing motion and moisture (February 2018)
  • El Cheapo Modules 14: Logarithmic RF Detector (March 2018)
  • El Cheapo Modules 16: 35-4400MHz frequency generator (May 2018)
  • El Cheapo Modules 17: 4GHz digital attenuator (June 2018)
  • El Cheapo: 500MHz frequency counter and preamp (July 2018)
  • El Cheapo modules Part 19 – Arduino NFC Shield (September 2018)
  • El cheapo modules, part 20: two tiny compass modules (November 2018)
  • El cheapo modules, part 21: stamp-sized audio player (December 2018)
  • El Cheapo Modules 22: Stepper Motor Drivers (February 2019)
  • El Cheapo Modules 23: Galvanic Skin Response (March 2019)
  • El Cheapo Modules: Class D amplifier modules (May 2019)
  • El Cheapo Modules: Long Range (LoRa) Transceivers (June 2019)
  • El Cheapo Modules: AD584 Precision Voltage References (July 2019)
  • Three I-O Expanders to give you more control! (November 2019)
  • El Cheapo modules: “Intelligent” 8x8 RGB LED Matrix (January 2020)
  • El Cheapo modules: 8-channel USB Logic Analyser (February 2020)
  • New w-i-d-e-b-a-n-d RTL-SDR modules (May 2020)
  • New w-i-d-e-b-a-n-d RTL-SDR modules, Part 2 (June 2020)
  • El Cheapo Modules: Mini Digital Volt/Amp Panel Meters (December 2020)
  • El Cheapo Modules: Mini Digital AC Panel Meters (January 2021)
  • El Cheapo Modules: LCR-T4 Digital Multi-Tester (February 2021)
  • El Cheapo Modules: USB-PD chargers (July 2021)
  • El Cheapo Modules: USB-PD Triggers (August 2021)
  • El Cheapo Modules: 3.8GHz Digital Attenuator (October 2021)
  • El Cheapo Modules: 6GHz Digital Attenuator (November 2021)
  • El Cheapo Modules: 35MHz-4.4GHz Signal Generator (December 2021)
  • El Cheapo Modules: LTDZ Spectrum Analyser (January 2022)
  • Low-noise HF-UHF Amplifiers (February 2022)
  • A Gesture Recognition Module (March 2022)
  • Air Quality Sensors (May 2022)
  • MOS Air Quality Sensors (June 2022)
  • PAS CO2 Air Quality Sensor (July 2022)
  • Particulate Matter (PM) Sensors (November 2022)
  • Heart Rate Sensor Module (February 2023)
  • UVM-30A UV Light Sensor (May 2023)
  • VL6180X Rangefinding Module (July 2023)
  • pH Meter Module (September 2023)
  • 1.3in Monochrome OLED Display (October 2023)
  • 16-bit precision 4-input ADC (November 2023)
  • 1-24V USB Power Supply (October 2024)
  • 14-segment, 4-digit LED Display Modules (November 2024)
  • 0.91-inch OLED Screen (November 2024)
  • The Quason VL6180X laser rangefinder module (January 2025)
  • TCS230 Colour Sensor (January 2025)
  • Using Electronic Modules: 1-24V Adjustable USB Power Supply (February 2025)
Circuit Surgery Regular Regular clinic clinic by by Ian Ian Bell Bell Topics in digital signal processing – digital-to-analog converter (DAC) frequency response W e are looking at various topics related to digital signal processing (DSP). DSP covers a wide range of electronics applications where signals are manipulated, analysed, generated, stored or displayed as digital data but originate from and/or are converted to real-world signals for interaction with humans or other parts of the physical world. Fig.1 shows the key elements of a generic DSP system with a signal path from an analog input via digital processing to an analog output. This does not necessarily represent every DSP system (not all have all the parts shown), but it serves are as reference for the various subsystems we will consider. Last month, we discussed the properties of the DAC output signal and the reconstruction filters required on DAC outputs. We described the LTspice behavioural sample-and-hold block that can be used to generate waveforms like those produced by DACs, for example, to use as input for simulation of reconstruction filters. We also discussed the fact that a DAC does not have a flat frequency response, which may need to be addressed in Analog Antialiasing filter In Sample and hold some DSP systems. We will continue with that theme this month. DAC frequency response recap As discussed last month, at first glance, it may seem that if we have a very good DAC operating at the original sampling frequency, a sufficient sampling rate (for the signal frequencies used) and a reconstruction filter with a flat passband and a sufficiently sharp cutoff, we can more-or-less perfectly reconstruct a sampled signal. However, this overlooks the fact that the shapes of an idealised sample waveform (a train of impulses) and the output from the DAC (stepped waveform) are not the same. That implies the DAC does not have a flat frequency response, which in turn means that even an ideal DAC and flat-passband brickwall lowpass reconstruction filter will not perfectly reproduce the sampled waveform. The shape of a DAC’s frequency response relates to the sinc mathematical function, which is defined as: sinc ( x )= sinc(0) is defined sin ( πfto /f sbe ) 1. The sinc function occurs abs frequently in DSP and ( Digital ADC sin ( x ) x Digital processing 1+ ) πf /f s RF RDAC G Analog Reconstruction filter Out RG RG +R F Fig.1: A generic digital signal processing (DSP) system structure. β= xs(f) DAC frequency Worst case response (sinc) attenuation 0 Original sampled response √ R21 + X 2C 1 DAC signal spectrum gain (linear) 1.0 2 2 ( R 1+ R 2 ) + X C 1 0.8 2 2 0.6 ( R1 + R2 ) +X C 1 2 2 0.4 √ R1 + X C1 0.2 R2 0.0 1+ f R1 2f s √ √ fs/2 fs Nyquist 1 = Fig.2: The DAC frequency response (sinc function) with af Lgeneric sampled signal 2 ( 2 π C 1 ) (2 R1 R 2+ R 22−R21) spectrum, using a linear scale for the DAC response. Practical Electronics | November | 2024 √ 1 2 π C1 ( R 1+ R 2) 1 telecommunications, where it is commonly written terms of πx rather than x. The frequency response of gain sin(variation (x) sinc ( xf ))= with frequency, of a DAC is given by: x abs ( ( )) sin πf /f s πf /f s RF frequency and abs(x) fs is the sampling 1+ value of x (ie, −x [making is the absolute RG a negative x positive] if x < 0, otherwise RG x; also written |x|). β= Fig.2 shows R the DAC frequency reG +R F sponse superimposed on a generic (and 2 2 R1 + X Csampled arbitrarily shaped) signal spec1 trum. The plot shows how the DAC 2 2 + Xsignal ( Rwith 1+ R 2)the C1 response aligns spectrum. Over the wanted range (up to fs/2), the 2 2 R2 ) +X C 1 ( R1 +frequency effect of the DAC’s response is to 2 2 attenuate the higher R1 +signal X C1 frequencies. To have no effect, it would have to be flat up R2 to fs­/2 which 1+is the maximum frequency R1 of the wanted (originally sampled) signal. Note that the DAC’s gain is zero at inte1 ger multiples f Lof = the sampling frequency. √ √ √ √ √ ( 2 π C 1 ) (2 R1 R 2+ R 22−R21) 2 Does it matter; what can we do? There are several1ways of dealing with + R 2) 2 π C1 ( R 1frequency a DAC’s sinc-shaped response. The simplest is to ignore the problem. 1 Although it is not very obvious in Fig.2, 2 π C1 R1 the impact of the DAC’s sinc-shaped frequency response is relatively small at lower frequencies. sinc(x) is close to 1 for small values of x, which corresponds frequencies well below the sampling frequency (where the term f/fs ­is small). In some systems, there is relatively little content in frequencies approaching fs ­/2, either because it is not present to a significant extent in the input signal, or because it has been removed by input filtering. In some cases, the acceptable level of signal fidelity does not merit the extra effort of dealing with the sinc response. In systems where the sinc shape of the DAC frequency response is a problem, a few approaches can be used to mitigate it. It is possible to correct for the DAC response using a filter with an equal and opposite frequency response to the DAC. 61 Digital Sample data Digital sinc pre-compensation filter Digital Analog Reconstruction filter DAC Sample data Out Fig.3: digital pre-equalisation frequency response correction. xs(f) Worst case DAC frequency attenuation response (sinc) 0 Original sampled signal spectrum fs/2 (Nyquist limit) fs Analog Reconstruction filter DAC Sampling rate and interpolation As noted previously, the effect of the DAC’s frequency response is worse at lower sampling rates relative to the DAC response gain (linear) 1.0 0.8 0.6 0.4 0.2 0.0 f original signal, so increasing the sampling rate will mitigate the effects of the DAC’s frequency response. The cyan line in Fig.2 highlights the worst attenuation due to the DAC frequency response, which occurs at the highest signal frequency. The original signal depicted in Fig.2 has a low amplitude at this frequency, but this is just a representative shape – the signal amplitude could easily be very significant at this frequency, implying a potentially large impact from the sinc attenuation. Fig.5 shows the same original signal sampled at a higher frequency. The relative shapes of the signal spectra and Digital Sample data Analogue Digital processing of data source Zero sample insertion Digital lowpass filter DAC fs Kfs Kfs Kfs Out Fig.4: analog post-equalisation frequency response correction. Fig.5: the same signal as in Fig.2 but sampled at a higher frequency, with a consequent reduction in DAC attenuation. This can be achieved using a digital filter before the DAC (referred to as a sinc precompensation or pre-equalisation filter), as shown in Fig.3. Alternatively, it can be achieved using an analog filter after the DAC and reconstruction filter (post-compensation or post-equalisation), as shown in Fig.4. These filters can flatten the frequency response but also worsen the signal-tonoise ratio at low frequencies. Analog sinc post-compensation filter Reconstruction filter Out Fig.6: a block diagram of an interpolating (or ‘oversampling’) DAC. Original sample points t Zero sample insertion t After filtering DAC response in this example result in much lower worse-case attenuation than for the situation in Fig.2. This scenario also puts less demand on the reconstruction filter. There is large gap between the wanted signal and the first spectral image of the sampled signal, so the reconstruction filter can roll off more slowly and achieve the same signal quality as a faster cutoff filter applied in the situation shown in Fig.2. The obvious approach to increasing the sampling frequency of the DAC may be to run the whole DSP system at this higher frequency. However, that may not be feasible due to resource/performance demands in other parts of the system, or the data sampling rate may be fixed for specific reasons, or it may be overkill just to achieve sinc compensation. A better solution may be to use an interpolating or ‘oversampling’ DAC. Such DACs change their outputs at a faster rate than the sampled data, achieving the same shift in DAC frequency response as running the whole system at the faster rate. Interpolation means finding the values of datapoints that we do not have in between the ones we do have. If the DAC is able to calculate new sample points, it can increase its sampling rate with the advantages just discussed. For example, if it can determine the value the signal has exactly halfway between the existing samples, the data rate can be doubled. In general, an interpolating DAC will increase the sampling rate by an integer multiple K, by inserting (K − 1) samples between each consecutive pair of existing samples. Multiples of 2, 4 and 8 are common, and interpolating DACs often have selectable values of K. A block diagram showing the structure of an interpolating DAC is shown in Fig.6, while some example waveforms (with K = 2) are shown in Fig.7. They operate by first inserting zero samples into the data between the existing data points. This produces a set of samples at the higher Kfs sampling rate, as shown in the middle waveform in Fig.7. To obtain the original waveform at the higher sampling rate, the zero-inserted sampled waveform is passed through a digital low-pass filter. Sinc correction filter example Fig.7: the basic principle of how an interpolating DAC works. 62 t We will now look at an example analog (post-equalisation) filter. Although a digital implementation may have more benefits, the analog approach is likely to Practical Electronics | November | 2024 Fig.8: a DAC equalisation filter needs a 1/sinc response to ƒs ­/2. be more familiar (we have not discussed digital filtering yet). Readers may also find the circuit useful in other contexts; for example, similar circuits are used in audio equalisation. We will consider a DAC with a sampling frequency of fs = 100kHz. Fig.8 shows a plot of the DAC sinc-shaped frequency response [absolute value of sinc(πf/fs ­)] and the reciprocal of this value, which are labelled as “sinc response” and “1/ sinc response”, respectively. The graph was plotted using Microsoft Excel, but other spreadsheets and mathematical apps could achieve the same thing. There is possible confusion over the units used in the sine function to calculate the sinc functions. They should be radians (the default in Excel), but the units for f and fs ­can be Hertz or radians per second, because the calculation uses a ratio (so unit scaling cancels). They must be in the same units, of course! We need to create a filter with a gain that matches the 1/sinc response, but there are a couple of points to consider before we decide exactly on how to do that. Firstly, the wanted signal only extends to at most fs /2, and usually has a lower maximum, as a real system will not be processing signals right up to the Nyquist limit. Secondly, the 1/sinc function be- Fig.9: an LTspice high-pass shelving filter for sinc equalisation. comes very large not required for this op amp model, but as we approach fs (it goes to infinity at would be needed if a real device model fs ); such large gains are neither practical (or the more advanced UniveralOpAmp nor desirable. version) was substituted. If the gain becomes too large, we risk Fig.10 shows the frequency response clipping the signal (if present at that of the circuit of Fig.9. The gain is unity frequency). There’s also the risk of pro(0dB) at frequencies below about 10kHz viding high-gain amplification of any and increases as the frequency increases, high-frequency noise from the previous levelling out at four times (12dB) above stage. Fortunately, we do not need to about 1MHz. This levelling off is the rematch the 1/sinc function in this range. quired shelving behaviour. To implement the specific 1/sinc reEqualisation filter circuit sponse of Fig.8, we have to match the The equalisation filter therefore reresponse of the circuit to the sinc funcquires a high-pass function, with a gain tion below approximately 50kHz. To do of 1 at low frequencies to provide the this, we need to some formulae to help flat response there. At higher frequencalculate circuit values. cies, the gain must increase but level off at some point rather than constantly The Fig.9 circuit is like a non­-inverting increasing. This is referred to as a highop amp amplifier (see Fig.11) the sinin ( xwhich ) sinc ( x )= are frequency­ pass shelving filter. A simple analog gain-setting components x implementation, which can be used as a dependent – hence the filtering action. post-equalisation filter, is shown in Fig.9 The gain of a basic non-inverting sin ( πf /f s ) op amp abs by the well-known (an LTspice schematic). amplifier is given πf /f s This circuit includes an idealised op formula: amp using the built-in UniveralOpAmp1 RF 1+ model with parameters (right click to RG set) Avol=10G, GBW=100G, Rin=100G and all others at zero. The supplies are RF is the feedback resistor value (the RG one between theβ= output inverting RG +Rand F input), while RG is the grounded resis2 2 tor value (from the input to R1 +inverting XC 1 ground). This is because the gain of the 2 2 circuit is equal to ( R1/β, ) + X C 1β is the 1+ R 2where fraction of the output signal fed back to 2 2 ( R1 + R2 ) +X C 1 the inverting input. ( ) √ √ √ √R +X 2 1 Vin + 1+ – R R2 R1 f L =F RG √ 2 C1 Vout 1 ( 2 π C 1 ) (2 R1 R 2+ R 22−R21) 2 1 2 π C1 ( R 1+ R 2) 1 Fig.10: the frequency response of the circuit in Fig.9. Practical Electronics | November | 2024 2 π C1 R1 amplifier Fig.11: a basic non-inverting made from an op amp and two resistors. 63 ( ( )) ( ) x πf /f s sin πf /f s abs R F πf /f s 1+ RG RF Similarly,1+ the total R effective resistance R G G divider formula to use in theβ= potential RG +R F for β is the root-square RG sum of the com2 β= bined resistors (R +2 R2) and XC1, that is: √ R1R+G1X+R C1 F abs sinc ( x )= sin ( x ) x The feedback is provided by the posin ( πf /f ) tential dividerabs formed by RFs and RG, and πf /fdivider the well-known potential formula s gives the value of β as the lower resistor RF (RG) divided by 1+the total resistance (RF R G + RG), that is: For the circuit in Fig.9, this is 1 + 300/100 = 4, or 12dB as seen in Fig.10. In general, we can choose two resistors to set the higher gain value. The capacitor then determines the frequency at which 2 2 the gain starts to increase. (RR21 +1+XR2C21) + X C 1 To design the filter, we could set the RG 22 22 β= lower cut-off frequency to match a point So, the gain(of the filter in Fig.7 (1/β) is: R + R +X (R11+ R 22)) + X CC11 RG +R F on the 1/sinc response curve. ‘Cutoff fre2 2 R + X2 C1 2 2 2 quency’ commonly refers to a 3dB change Taking 1/β gives ( R1 + R1 2 ) +X C1 R1 +the X C 1gain formula. in gain, but this is by definition rather R2 2 2 2 1+ R1 + X C1 2 than a fundamental rule; some filters Filter formulae ( R 1+ R 2 ) + X C 1 R1 sin ( x ) cum- use a different definition. For the filter, the lower sin divider resistor This is unfortunately a somewhat R 2 (2x ) 2 1+ sinc ( x )= x 1 sinc The shelving filter can have two bersome formula. is replaced by the of +( xR)2= +XxC 1 ( R1series ) combination R1 f = 2 the value2 of 2 cutoff frequencies defined: a lower one R1 and C1. This is an2 impedance At very lowL frequencies, (call it 2 C 1 )( πf ( 2 πsin (2/fR1s )RimpedR1 + X resistance. 2+ R 2−R1) (fL), where the gain first rises a certain XC1 is very largeabs Z1) rather than a simple (a capacitor’s 1 sin ( πfC1/f s ) f = abs L as frequency πf /f 2 A full analysis can be done using Laance increases decreases). amount (eg, by 3dB above 0dB), and an 2 2 1 s R2 /f s ( 2 π C 1 ) (2 Rthat 1 R 2+ R 2−R1) 1+circuitπf place transform values, but as we The large value of (XRC1+means upper one (fU), a certain amount below the reR 2 π C 1 R 1 2) R1 only need to calculate little 1 Feffect on the total the high frequency level-off (eg, 3dB RF the magnitude sistors have very1+ 1+ (not the phase), R G roots, so they can below 12dB). of the impedance we value inside 2the 1 π C1square 1 ( R 1+ R 2) f L = R G of Z2 in place of2 R 2 π C can use the magnitude be ignored. Removing them causes the Shelving filters may have less than 2 1 1 R 2Rπ C 1 ) 1(2for R1 β. R 2This + R 2−R1two ) XC1 terms to1β= 6dB difference between the two level lower resistor in the( formula cancel.GSo, the gain at G β= RG +R(0dB), F gains, so 3dB cutoff definition may not is given by: low frequencies as seen 2 π Cis 1 Runity 1 R1G +R F be appropriate; however, in this case, it in Fig.10. 2 2 2 π C21 ( R 12+ R 2) R1 + X C 1 is fine. Furthermore, the sinc frequency At very high frequencies, the value R1 + X C 1 2 2 to zero, 1 response for a 100kHz DAC is down by of X is very small – it tends C1 2 ( R 1+ R 2 ) + X C 1 R1reactance + R ) + X 2C(effective 3dB at about 44.2kHz, which is a good Here, XC1 is2the so we can remove it from the equation, 1 π( C 1 R1 2 2 2 as the portion of the Nyquist frequency and and the gain becomes the same resistance) of C1. Note that we have to 2 2 ( R1 + R2 ) +X C 1 R1 + Rthese 2 ) +Xtwo C 1 values may be a suitable starting point to try to inverting amplifier, with R square, sum and(root as R and F 2 21 R1 + X C1 2 match the 1/sinc and filter gains. – they cannot just R be2 +added, like we R2 as RG, that is: X 1 C1 +3dB corresponds to a gain of √2. If we could do for two resistors in series. The R2 R 2 of value C is XC 1+ reactance of a capacitor equate the filter gain expression above to 1+ R1 √ 2, we can solve for f to find the lower = 1 ÷ (2πfC). R1 ( ) √ √√ √ √ √ √ √ √ √ ( √( √ ) ) √ √ √ √ √ √ √ √ f L= √ 1 ( 2 π C 1 ) (2 R1 R 2+ R 22−R21) 2 1 2 π C1 ( R 1+ R 2) 1 2 π C1 R1 Fig.12: the equalisation filter response compared with 1/sinc. √ f L= √ 1 ( 2 π C 1 ) (2 R1 R 2+ R 22−R21) 2 1 2 π C1 ( R 1+ R 2) 1 2 π C1 R1 Fig.13: DAC frequency response with various equalising filters. 1557 Polycarbonate IP68 Learn more: hammondmfg.com/1557 uksales<at>hammfg.com • 01256 812812 64 Practical Electronics | November | 2024 √( R + R ) + X √( R + R ) +X 1 2 1 2 2 √R +X 2 1 √R +X 1 C1 2 C1 1+ 2 C1 R 2 frequency. After a bit of al3dB cutoff 1+ get: gebra, we R1 f L= √ C1 R2 R1 √ 1 = gain slope which causesf Lthe to increase. 2 2 2 There is a pole at:( 2 π C 1 ) (2 R1 R 2+ R 2−R1) 1 2 π C1 ( R 1+ R 2) 1 sin ( x ) sinc 2 ( x )= ( 2 π C 1 ) (2 R1 R 2+xR 22−R21) This is the higher frequency corner 1 1 sin (equation πf /f s ) allows which causes2 the gain slope to decrease Conveniently, this R π C 1 1 abs C , so we can find a and hence level off. us to2 π swap R 2) 1 πf /f s C1 ( Rf1L+and capacitor for a required cutoff (assum1 RF chosen the values Matching the 1/sinc response ing we have already 1+ the upper gain). 2 πand C1 RR2 of R1 Fig.12 shows the equalisation filter 1 to set RG Using the resistor values from Fig.7 response (with the values as in Fig.7) RG and fL = 44.2kHz β=gives C1 = 9.6nF. This added to the sinc function plots. This was obtained by calculating the filter gain is close to the value inF Fig.7, but as RG +R equation given above in Excel. we will see shortly, slightly different 2 2 R1 + X C 1 optimal. HowThis confirms a close match to the values may prove more required 1/sinc up to near the Nyquist ever, this gives us the something in the 2 2 ( R 1+ R 2 ) + X C 1 frequency, so basically it fulfils our reright range. quirements. Once this is set up in Excel, Other values we can 2use 2to charac( R1 + R2 ) +Xin C 1 a filter’s it is easy to tweak the capacitor or resisterise the key frequencies 2 2 response are the poles R1 +and X C1zeros. These tor values to see how they influence the matching of the responses. have a specific definition related to LaR 2 of the frequency The purpose of the equalisation filter is place domain analysis 1+ R1 to compensate for the attenuation caused response, and determine the ‘corner’ by the DAC’s frequency response. Fig.13 frequencies at which the slope of the 1 shows the response of the 100kHz DAC gain magnitude changes. f L= 2 2 R 22−Rconsidered in this example together After a zero, the slope ( 2 π C 1increases ) (2 R1 R 2+by 1) with the combined response of the DAC 20dB per decade, and after a pole, it 1 and equalisation filter from Fig.9, with decreases by 20dB per decade. For the R 1a+zero R 2) at: 2 π C ( C1 = 8.8nF and C1 = 7.8nF. Again, the filter in Fig.7, there1 is plots were produced in Excel, with the 1 combined responses being obtained by 2 π C1 R1 multiplying the DAC’s sinc function and This is the lower frequency corner filter gain at each frequency. ( ) √ √ √ √ √ Simulation files Most months, LTSpice is used to support descriptions and analysis in Circuit Surgery. The examples and files are available for download from the PE website: https://bit.ly/pe-downloads This is plotted in dB by calculating 20log10(G) for each gain value G in Excel. In both cases, with the filter added, the attenuation at higher frequencies is reduced, showing that the equalisation filter is doing its job. The gain of the DAC-plus-filter remains within a fraction of a decibel of 0dB to frequencies much closer to the Nyquist frequency than with just the DAC. Fig.13 also illustrates that that we can have different shapes for the combined DAC and equalisation filter response. With C1 = 7.8nF, we get a very flat response, within ±0.015dB of 0dB to beyond 20kHz. With C1 = 8.8nF, the response remains within ±0.2dB to beyond 40kHz but is less flat than the 7.8nF case. Using C1 = 9.6nF as calculated above to match the 3dB points give an even more peaked response. Peaked responses for a DAC-plus-filter like this may be useful because they can help to compensate for the roll-off of the reconstruction filter near its cutoff frequency. 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